GCIXP1250BC Intel, GCIXP1250BC Datasheet - Page 12

• Manufacturer Part Number: GCIXP1250BC
• Description: IC MPU NETWORK 232MHZ 520-BGA
• Manufacturer: Intel

Specifications of GCIXP1250BC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 520-BGA
• Pin Count: 520
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 837414

Intel
Errata
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12
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IXP1250 Network Processor
Clock Setup Time
Because the SRAM and SDRAM setup times are directly related to the loading of SCLK and
SDCLK, excessive setup times (T
value of T
Inability to meet the data setup time specification for memory devices.
Buffer SCLK and SDCLK with a zero skew clock buffer such as a Cypress CY2309.
NoFix
Hold Time Issues for all PCI Signals (Both Bused and Control)
The PCI Local Bus Specification, Revision 2.2, specifies a minimum Hold Time of 0 ns in Section
7.6.4.2. The IXP1250 requires a minimum hold time of 1.0 ns (t
Clk).
System designers must constrain their design to tighter than worst-case PCI timing. One recom-
mendation is to limit the trace length of the PCI bus resulting in a reduction of Tprop.
None.
NoFix
IX Bus Contention in Shared IX Bus Mode
In shared IX Bus mode, using the TK_IN pin to configure the initial IX Bus Owner and Ready Bus
Master Mode could result in improper initialization. As a result, more than one IXP1250 may be
the initial IX Bus Owner and Ready Bus Master.
This erratum causes contention on the IX Bus and the Ready Bus. It is also possible that the devices
could initialize to the opposite state (not initial IX Bus Owner, Ready Bus Slave), in which case no
device controls the Ready Bus as master.
Use software to configure the initial IX Bus Owner and Ready Bus Master Mode instead of using
the TK_IN strapping option. Pulldown the TK_IN inputs to all IXP1250s on a Shared IX Bus to
inhibit initial IX Bus Owner and Ready Bus Master Mode. This ensures that no IXP1250 will be
the initial IX Bus Owner and that all IXP1250s will be Ready Bus slaves. Boot software can then
initialize one IXP1250 to initial IX Bus Owner and Ready Bus Master Mode by writing
RDYBUS_TEMPLATE_CTL[8]=1. It is recommended to perform this operation as quickly as
possible after reset to minimize the length of time the IX Bus and Ready Bus float.
NoFix
Tval max Timing Issues When Running at 66 MHz for all PCI Signals
The PCI Local Bus Specification, Revision 2.2 specifies a maximum Signal Valid Delay (Tval)
time of 6.0ns in Section 7.6.4.2. The IXP1250 guarantees a worst-case Tval maximum of 6.5 ns.
The Tval maximum value of 6.5 ns requires a reduction in maximum flight time (Tprop) when
running at 66 MHz.
System designers must constrain their design to tighter than worst-case PCI timing. One recom-
mendation is to limit the trace length of the PCI bus resulting in a reduction of Tprop.
NoFix
su
for both memory interfaces is 7.5 ns.
su
) may be seen under heavy loading conditions. The maximum
h
- Input Signal Hold Time from
Specification Update