IDT79RC32T355-133DH IDT, Integrated Device Technology Inc, IDT79RC32T355-133DH Datasheet - Page 12

• Manufacturer Part Number: IDT79RC32T355-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T355-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T355-133DH

Boot Configuration Vector
ation when cold reset is complete.
U1CTSN
MDATA[2:0]
MDATA[3]
MDATA[4]
MDATA[5]
MDATA[7:6]
MDATA[8]
MDATA[9]
MDATA[10]
1.
2. 2
IDT 79RC32355
Schmitt Trigger Input.
The boot configuration vector is read into the RC32355 during cold reset. The vector defines parameters in the RC32355 that are essential to oper-
The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.
I
2
Signal
C - Bus Specification by Philips Semiconductors.
Name
Clock Multiplier. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock.
0x0 - multiply by 2
0x1 - multiply by 3
0x2 - multiply by 4
0x3 - reserved
0x4 - reserved
0x5 - reserved
0x6 - reserved
0x7 - reserved
Endian. This bit specifies the endianness of RC32355.
0x0 - little endian
0x1 - big endian
Reserved. Must be set to 0.
Debug Boot Mode. When this bit is set, the RC32355 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset.
0x0 - regular mode (processor begins executing at 0xBFC0_0000)
0x1 - debug boot mode (processor begins executing at 0xFF20_0200)
Boot Device Width. This field specifies the width of the boot device.
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
0x2 - 32-bit boot device width
0x3 - reserved
EJTAG/ICE Interface Enable. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are
selected.
0x0 - GPIOP[31, 13:10] pins behaves as GPIOP
0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N,
Fast Reset. When this bit is set, RC32355 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation.
0x0 - Normal reset: RC32355 drives RSTN for minimum of 4096 clock cycles
0x1 - Fast Reset: RC32355 drives RSTN for 64 clock cycles (test only)
DMA Debug Enable. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory
and peripheral bus DMA transactions.
0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP
0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0]
Type I/O Type
GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and
GPIOP[13] pin behaves as EJTAG_DCLK
I
STI
UART channel 1 clear to send.
Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace clock, EJTAG_DCLK.
Table 2 Boot Configuration Vector Encoding (Part 1 of 2)
Table 1 Pin Descriptions (Part 8 of 8)
12 of 47
Name/Description
Description
May 25, 2004