IDT79RC32T355-133DH IDT, Integrated Device Technology Inc, IDT79RC32T355-133DH Datasheet - Page 9

• Manufacturer Part Number: IDT79RC32T355-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T355-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T355-133DH

DMAREQN
DMADONEN
USB
USBCLKP
USBDN
USBDP
USBSOF
Ethernet
MIICOLP
MIICRSP
MIIMDCP
MIIMDIOP
MIIRXCLKP
MIIRXDP[3:0]
MIIRXDVP
MIIRXERP
MIITXCLKP
MIITXDP[3:0]
MIITXENP
MIITXERP
I
SCLP
SDAP
EJTAG
JTAG_TCK
JTAG_TDI
JTAG_TDO
2
C
IDT 79RC32355
Name
Type I/O Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Low Drive USB start of frame.
Low Drive MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management inter-
Low Drive
Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission.
Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols
Low Drive
Low Drive
Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this
with STI
with STI
with STI
USB
USB
STI
STI
STI
STI
STI
STI
STI
STI
STI
STI
STI
STI
External DMA Device Request. The external DMA device asserts this pin low to request DMA service.
Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18].
External DMA Device Done. The external DMA device asserts this signal low to inform the RC32355 that it is done with
the current DMA transaction.
Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19].
USB Clock. 48 MHz clock input used as time base for the USB interface.
USB D- Data Line. This is the negative differential USB data signal.
USB D+ Data Line. This is the positive differential USB data signal.
Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].
MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected.
MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.
face.
MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the
ethernet PHY.
MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data.
MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.
MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus.
MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-
rently being sent in the MII receive data bus.
MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
which are not valid data or delimiters.
I
Primary function: General purpose I/O, GPIOP[15]. At reset, this pin defaults to primary function GPIOP[15].
I
Primary function: General purpose I/O, GPIOP[14]. At reset, this pin defaults to primary function GPIOP[14].
JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an
external resistor, listed in Table 16.
JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,
listed in Table 16. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to
switch the PC trace mode off.
signal is tri-stated. This signal requires an external resistor, listed in Table 16. This is also used to output the EJTAG_TPC
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.
2
2
C Interface Clock. An external pull-up is required on SCLP, see the I
C Interface Data Pin. An external pull-up is required on SDAP, see the I
Table 1 Pin Descriptions (Part 5 of 8)
9 of 47
Description
2
C spec.
2
C spec.
2
2
May 25, 2004