MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet - Page 55

• Manufacturer Part Number: MPC8560CPX667JC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8560CPX667JC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Rohs Compliant: No
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

12.2 PCI/PCI-X AC Electrical Specifications
This section describes the general AC timing parameters of the PCI/PCI-X bus of the MPC8560. Note that
the SYSCLK signal is used as the PCI input clock.
66 MHz.
Freescale Semiconductor
SYSCLK to output valid
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
Input hold from SYSCLK
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
1.Note that the symbols used for timing specifications herein follow the pattern of t
2.See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
4.Input timings are measured at the pin.
5.The timing parameter t
6.The setup and hold time is with respect to the rising edge of HRESET.
7.The timing parameter t
8.The reset assertion timing requirement for HRESET is 100 μs.
9.Guaranteed by characterization.
10.Guaranteed by design.
block)(signal)(state) (reference)(state)
For example, t
valid state (V) relative to the SYSCLK clock, t
t
frame signal (F) going to the valid (V) state.
delivered through the component pin is less than or equal to the leakage current specification.
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see
Bus Specifications .
PCRHFV
Section 15,
symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the
PCIVKH
Parameter
9
“Clocking.”
setup time
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
SYS
PCRHFV
symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the
Table 43. PCI AC Timing Specifications at 66 MHz
indicates the minimum and maximum CLK cycle times for the various specified
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
for inputs and t
SYS
(first two letters of functional block)(reference)(state)(signal)(state)
, reference (K) going to the high (H) state or setup time. Also,
Symbol
t
t
t
t
t
t
PCKHOV
t
t
PCRHRX
PCKHOX
PCKHOZ
PCRVRH
PCRHFV
PCIVKH
PCIXKH
Table 43
1
provides the PCI AC timing specifications at
10 × t
Min
2.0
3.0
—
—
10
0
0
SYS
(first two letters of functional
Max
6.0
14
50
—
—
—
—
—
clocks
clocks
Unit
ns
ns
ns
ns
ns
ns
for outputs.
2, 3, 10
5, 6, 10
Notes
2, 4, 9
2, 4, 9
6, 10
7, 10
2, 9
2
PCI/PCI-X
55