MC68360EM33L Freescale Semiconductor, MC68360EM33L Datasheet - Page 373

• Manufacturer Part Number: MC68360EM33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Both internal and external request modes can be used to start a transfer when the single
address mode is selected (see Figure 7-15). The ECO bit in the CMR controls whether a
source read or a destination write cycle occurs on the data bus. If the ECO bit is set, the
external handshake signals are used with the source operand, and a single address source
read occurs. If the ECO bit is cleared, the external handshake signals are used with the des-
tination operand, and a single address destination write occurs.
Single Address Source Read. During the single address source read cycle, the device or
memory selected by the address in the SAPR, the source function codes in the FCR, and
the size in the CMR provides the data and control signals on the data bus. This bus cycle
operates like a normal read bus cycle. The destination device is controlled by the IDMA
handshake signals (DREQx, DACKx, and DONEx). The assertion of DACKx provides the
write control to the destination device. For more details about the IDMA handshake signals,
see 7.6.3 Interface Signals.
Single address mode does not support access to the internal
dual port ram of MC68360. In order to transfer from/to internal
dual port ram, user should use dual address mode.
CYCLE STEAL
BURST MODE
(OUTPUT)
REQUEST
REQUEST
NOTE:
(OUTPUT)
(OUTPUT)
DSACKx
1. This example assumes the peripheral is being written. If the peripheral is being read,
2. This example shows the operation of DREQ in two different modes.
3. This example assumes that SRM = 0 in the CMR. Otherwise, DREQx would not be
(INPUT)
CLKO1
(INPUT)
DREQx
DREQx
DACKx
R/W would be low during the transfers.
recognized by the IDMA until it had been sampled on two consecutive falling edges of
the clock.
(I/O)
AS
R/W
Figure 7-15. Single Address Mode Timing
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
CYCLE STEAL
REQUEST
DREQ SAMPLED
LOW
OTHER CYCLE
S2
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
S0
CONTINUE
NOTE
PERIPHERAL WRITE
BURST
MEMORY READ
S2
IDMA
TRANSFER
ANOTHER
S4
S0
PERIPHERAL WRITE
MEMORY READ
S2
IDMA
STOP
BURST
S4
S0
IDMA Channels