MC68360EM33L Freescale Semiconductor, MC68360EM33L Datasheet - Page 525

• Manufacturer Part Number: MC68360EM33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The physical layer of the BISYNC communications link must provide a means of synchro-
nizing the receiver and transmitter. This is usually accomplished by sending at least one pair
of synchronization characters prior to every frame
BISYNC is unusual in that a transmit underrun need not be an error. If an underrun occurs,
the synchronization pattern is transmitted until data is once again ready to transmit. The
receiver discards the additional synchronization characters as they are received. In non-
transparent operation, all synchronization characters (SYNCs) are discarded. In transparent
operation, all DLE-SYNC pairs are discarded. (Correct operation in this case assumes that,
on the transmit side, the underrun does not occur between the DLE and its following char-
acter, a failure mode that is prevented in the QUICC.)
By appropriately setting the SCC mode register, any of the SCC channels may be config-
ured to function as a BISYNC controller. The BISYNC controller handles the basic functions
of the BISYNC protocol in normal mode and in transparent mode.
The SCC in BISYNC mode can work with the TSA or NMSI. The SCC can support modem
lines by a connection to the port C pins or by using the general-purpose I/O pins.
The BISYNC controller consists of separate transmit and receive sections whose operations
are asynchronous with the CPU32+ core and may be either synchronous or asynchronous
with respect to the other SCCs.
7.10.20.1 BISYNC CONTROLLER FEATURES. The BISYNC controller contains the fol-
lowing key features:
7.10.20.2 BISYNC CHANNEL FRAME TRANSMISSION. The
designed to work with almost no intervention from the CPU32+ core. When this CPU32+
core enables the BISYNC transmitter, it will start transmitting SYN1–SYN2 pairs (located in
the data synchronization register) or idle as programmed in the BISYNC mode register. The
BISYNC controller polls the first BD in the transmit channel’s BD table. If there is a message
• Flexible Data Buffers
• Eight Control Character Recognition Registers
• Automatic SYNC1–SYNC2 Detection
• 16-Bit Pattern (BISYNC)
• 8-Bit Pattern (Monosync)
• 4-Bit Pattern (Nibblesync)
• External Sync Pin Support
• SYNC/DLE Stripping and Insertion
• CRC16 and LRC Generation/Checking
• Parity (VRC) Generation/Checking
• Supports BISYNC Transparent Operation (Use of DLE Characters)
• Maintains Parity Error Counter
• Reverse Data Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
BISYNC
transmitter
is