MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 347

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

REF—Output Reference Event
CAP—Capture Event
7.5.3 Timer Examples
The following example lists the required initialization sequence of timer 2 to generate an in-
terrupt every 10 s, assuming a general system clock of 25 MHz. This means that an inter-
rupt should be generated every 250 system clocks.
To implement the same function with a 32-bit timer using timer 1 and timer 2, the following
sequence may be used:
MOTOROLA
The counter has reached the TRR value. The ORI bit in the TMR is used to enable the
interrupt request caused by this event.
The counter value has been latched into the TCR. The CE bits in the TMR are used to
enable generation of this event.
1. TGCR = $0000. Put timer 2 into the reset state. Do not use cascaded mode.
2. TMR2 = $001A. Enable the prescaler of the timer to divide-by-1 and the clock source
3. TCN2 = $0000. Initialize the timer 2 count to zero. This is the default state of this reg-
4. TRR2 = $00FA. Initialize the timer 2 reference value to 250 (decimal).
5. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
6. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initial-
7. TGCR = $0010. Enable timer 2 to begin counting.
1. TGCR = $0080. Cascade timer 1 and timer 2. Put timer 1 and timer 2 in the reset state.
2. TMR2 = $001A. Enable the prescaler of timer 2 to divide-by-1 and the clock source to
3. TMR1 = $0000. Enable timer 1 to use the output of timer 2 as its input, which is the
4. TCN1 = $0000, TCN2 = $0000. Initialize the combined timer 1 and timer 2 count to
5. TRR1 = $0000, TRR2 = $00FA. Initialize the combined timer 1 and timer 2 reference
6. TER2 = $FFFF. Clear TER2 of any bits that might have been set.
7. CIMR = $00040000. Enable the timer 2 interrupt in the CPM interrupt controller. Initial-
8. TGCR = $0091. Enable timer 1 and timer 2 to begin counting. Leave the timers in cas-
to general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10- s interrupts.
ister.
ize the CPM interrupt configuration register.
general system clock. Enable an interrupt when the reference value is reached, and
restart the timer to repeatedly generate 10 s interrupts.
default state of this register.
zero which is the default state of this register. (This can be accomplished with one 32-
bit data move to TCN1.)
value to 250 (decimal). (This can be accomplished with one 32-bit data move to
TRR1.)
ize the CPM interrupt configuration register.
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Timers
7-23