MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 782

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Applications
9.6.5 Hardware Configuration
The following paragraphs describe the hardware configuration of the SCSI controller inter-
face. Figure 9-21 shows the SCSI bus interface.
9.6.5.1 CLOCKING STRATEGY. In this application, the system clock is generated from a
32.768-kHz crystal into the QUICC. The QUICC internal PLL multiplies the frequency up to
25 MHz and outputs 25 MHz on CLKO1, which is fed into the 53C90 CLK input. CLKO2,
which has 50 MHz available, might be disabled in software to save power. It is also possible
to run the QUICC at 20 MHz and feed the 53C90 40 MHz from CLKO2 to achieve fast SCSI
synchronous mode. In that mode, make sure the prescale bit in the clock conversion register
($09) of the 53C90 is set. Timing issues also need to be considered.
The use of the 32.768-kHz crystal is not a requirement but is a low-cost solution. A 25-MHz
external oscillator can also be used. The QUICC clocking section allows for the clock oscil-
lator to be kept running through the VDDSYN pin in a power-down situation, if desired.
9.6.5.2 RESET STRATEGY. If a pushbutton switch is needed, it can be connected by an
open-drain buffer to the QUICC RESETH line, once debounced. The QUICC reset control
logic asserts RESETH for a minimum of 512 cycles (20.48 s at 25 MHz); this is inverted
and routed to the 53C90 reset input since it is an active-high reset.
9.6.5.3 READ/WRITE TIMING. The CPU32+ is running three clock cycles on a normal
zero-wait-state bus cycle, implying 120 ns for the read or write bus cycle (f = 25 MHz, clock
period is 40 ns). Looking at the QUICC read timing, the read strobe (OE) is asserted after
the falling edge of S0. Electrical specification 9 can be as long as 20 ns. From the time the
read strobe is asserted until data is valid from the 53C90 can be as long as 70 ns, giving a
total time of 90 ns, which would occur after the falling edge of S4 where the data should be
read. Therefore, one wait state should be inserted on the read cycle. Cycle time is also
important. The 53C90 needs a minimum of 40 ns before the next read; whereas, the QUICC
guarantees a minimum of 30 ns. TRLXQ and CSNTQ bits in the base register of the QUICC
chip select should be set to ones to relax the timing and allow successive reads.
Using WE0 as the strobe for the write cycle, the CPU32+ will guarantee a minimum hold time
of 35 ns; the 53C90 needs 2 ns. The setup time is a 35-ns minimum for the QUICC; the
53C90 needs 11 ns. Therefore, no wait states are needed for the write cycle, but cycle time
is an issue. The 53C90 needs a minimum of 60 ns before the next write; whereas, the
CPU32+ guarantees 35 ns. Again, set the TRLXQ and CSNTQ bits to one to relax the timing
and allow successive writes
9.6.5.4 INTERRUPT HANDLING. There are multiple SCSI instructions that would generate
an interrupt to the QUICC. Since the 53C90 does not put a vector on the bus, it will use
AVEC to terminate the bus cycle and generate an automatic vector number. This interrupt
is coming in at IRQ2, leading to a vector number of 24 + 2 = 26 ($1A). The autovector reg-
ister should be initialized to handle an autovector on IRQ2. When the QUICC is interrupted,
the interrupt service routine should read the status register and sequence step register of
the 53C90 before reading the interrupt register. Reading the interrupt register resets the
interrupt pin (INT), the contents of the sequence step register, bits 7–3 of the status register,
and the contents of the interrupt register itself.
9-62
MC68360 USER’S MANUAL
MOTOROLA
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