CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet - Page 28

• Manufacturer Part Number: CS4265-CNZ
• Description: IC CODEC 24BIT 104DB 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4265-CNZ

• Package / Case: 32-QFN
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2S)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1001 - BOARD EVAL FOR CS4265 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1039

28
4.8
4.9
4.10
DAC Serial Data Input Multiplexer
The CS4265 contains a 2-to-1 serial data input multiplexer. This allows two separate data sources to be
input into the DAC without the use of any external multiplexing components.
Source (Bit 7)” on page
De-Emphasis Filter
The CS4265 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in
changes in sample rate, Fs. Please see
phasis control.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction.
De-emphasis is only available in Single-Speed Mode.
Internal Digital Loopback
The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input
of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See
Selection - Address 06h” section on page
When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4265.
Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until
the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the
format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin
in the format selected by the ADC_DIF bit in register 04h.
clocking change, the DAC outputs will always be in a zero-data state. If non-zero serial audio input is
present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes
to its zero-data state.
Figure
-10dB
Gain
0dB
39” describes the control port settings necessary to control the multiplexer.
dB
13. The frequency response of the de-emphasis curve scales proportionally with
Figure 13. De-Emphasis Curve
3.183 kHz
T1=50 µs
Section 6.3.3 “De-Emphasis Control (Bit 1)” on page 37
F1
39).
10.61 kHz
F2
T2 = 15 µs
Frequency
“Section 6.6.1 “DAC SDIN
CS4265
for de-em-
DS657F2
“Signal