CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet - Page 36

IC CODEC 24BIT 104DB 32QFN

CS4265-CNZ

Manufacturer Part Number
CS4265-CNZ
Description
IC CODEC 24BIT 104DB 32QFN
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS4265-CNZ

Package / Case
32-QFN
Data Interface
PCM Audio Interface
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
104 / 104
Voltage - Supply, Analog
3.13 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
4
Number Of Dac Outputs
2
Conversion Rate
192 KSPS
Interface Type
Serial (I2S)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 95 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1001 - BOARD EVAL FOR CS4265 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1039

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36
6.2.4
6.2.5
6.3
6.3.1
6.3.2
Reserved
7
DAC Control - Address 03h
Power-Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital In-
terface Format and the options are detailed in
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is
active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs
will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the
DACSoft and DACZero bits in the DAC Control 2 register.
DAC_DIF1 DAC_DIF0
0
0
1
1
Reserved
6
0
1
0
1
DAC_DIF1
5
Left Justified, up to 24-bit data (default)
Table 6. DAC Digital Interface Formats
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
DAC_DIF0
I²S, up to 24-bit data
Description
4
Table 6
Reserved
3
and
Figures
MuteDAC
5-7.
2
Format
0
1
2
3
DeEmph
1
Figure
5
6
7
7
CS4265
Reserved
DS657F2
0

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