CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet - Page 35

• Manufacturer Part Number: CS4265-CNZ
• Description: IC CODEC 24BIT 104DB 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4265-CNZ

• Package / Case: 32-QFN
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2S)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1001 - BOARD EVAL FOR CS4265 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1039

DS657F2
6. REGISTER DESCRIPTION
6.1
6.2
6.2.1
6.2.2
6.2.3
PART3
Freeze
7
7
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1101b (0Dh), and the remaining
bits (3 through 0) indicate the device revision as shown in
Power Control - Address 02h
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
Table
Reserved
PART2
5.
6
6
Reserved
PART1
MuteDAC
MuteADC
Gain[5:0]
Gain[5:0]
Vol[7:0]
Vol[7:0]
TxMute
Name
5
5
REV[2:0]
001
010
011
Table 4. Device Revision
Table 5. Freeze-able Bits
Reserved
PART0
4
4
Register
0Ah
0Bh
0Eh
03h
04h
07h
08h
PDN_MIC
REV3
3
3
Revision
Table 4
B, C0
C1
A
PDN_ADC
below.
REV2
2
2
Bit(s)
5:0
5:0
7:0
7:0
2
2
4
PDN_DAC
REV1
1
1
CS4265
REV0
PDN
0
0
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