CS4245-CQZ Cirrus Logic Inc, CS4245-CQZ Datasheet - Page 36

IC CODEC AUD STER 104DB 48LQFP

CS4245-CQZ

Manufacturer Part Number
CS4245-CQZ
Description
IC CODEC AUD STER 104DB 48LQFP
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS4245-CQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
104 / 104
Voltage - Supply, Analog
3.13 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
12
Number Of Dac Outputs
4
Conversion Rate
192 KSPS
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 95 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1501 - BOARD EVAL FOR CS4245 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1034

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36
4.12
4.12.1 SPI Mode
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
The MUTEC pin is an active-low CMOS driver. See
Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS4245 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
In SPI Mode, CS is the CS4245 chip-select signal; CCLK is the control port bit clock (input into the CS4245
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
CS4245
shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
MUTEC
AOUT
Figure 16. Suggested Active-Low Mute Circuit
LPF
+V
-V
EE
EE
Figure 16
Couple
AC
MMUN2111LT1
+V
A
-V
47 kΩ
for a suggested active-low mute circuit.
EE
10 kΩ
560 Ω
2 kΩ
Audio
Out
CS4245
DS656F2

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