CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 24

IC CODEC AC97 I2S 48-LQFP

CS4205-KQZ

Manufacturer Part Number
CS4205-KQZ
Description
IC CODEC AC97 I2S 48-LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codec '97r
Datasheet

Specifications of CS4205-KQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
18, 20 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
90 / 90
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
8
Number Of Dac Outputs
3
Conversion Rate
48 KSPs
Interface Type
Serial (5-Wire)
Resolution
18 bit, 20 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Number Of Channels
1 ADC, 1 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1182

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4205-KQZ
Manufacturer:
Vishay
Quantity:
718
Part Number:
CS4205-KQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS4205-KQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
4.3
The CS4205 is designed to handle SYNC protocol
violations. The following are situations where the
SYNC protocol has been violated:
24
The SYNC signal is not sampled high for exact-
ly 16 BIT_CLK clock cycles at the start of an
audio frame.
The SYNC signal is not sampled high on the
256th BIT_CLK clock period after the previous
SYNC assertion.
AC-Link Protocol Violation - Loss of
SYNC
Upon loss of synchronization with the controller,
the CS4205 will ‘clear’ the Codec Ready bit in the
serial data input frame until two valid frames are
detected. During this detection period, the CS4205
will ignore all register reads and writes and will
discontinue the transmission of PCM capture data.
In addition, if the LOSM bit in the Misc. Crystal
Control Register (Index 60h) is ‘set’ (default), the
CS4205 will mute all analog outputs. If the LOSM
bit is ‘clear’, the analog outputs will not be muted.
The SYNC signal goes active high before the
256th BIT_CLK clock period after the previous
SYNC assertion.
CS4205
DS489PP4

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