CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 51

• Manufacturer Part Number: CS4205-KQZ
• Description: IC CODEC AC97 I2S 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4205-KQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPs
• Interface Type: Serial (5-Wire)
• Resolution: 18 bit, 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1182

5.35
E[15:0]
Default
The BDI Config Register (Index 6Eh, Address 0Ch) enables BIOS-Driver communication for each possible event. If a
The BDI Wakeup Register (Index 6Eh, Address 0Dh) provides a mask for determining if a BDI event will generate a
5.36
ZVEN
LOCK
Ph[24:0]
Default
5.37
E[15:0]
bit is ‘0’, the corresponding event will not be communicated. If a bit is ‘1’, the corresponding event will be communicated
by asserting the BDI bit in input slot 12. If an event occurs, the BIOS will ‘set’ the corresponding bit in the BDI Status
Register (Index 7Ah). This bit remains ‘set’ until it is cleared by the driver, acknowledging the event has been handled.
This behavior is equivalent to “non-sticky” (level sensitive) GPIO input pins.
wakeup or GPIO_INT. If a bit is ‘0’, the corresponding event will not generate an interrupt. If a bit is ‘1’, the corresponding
event will generate an interrupt. Refer to the GPIO Pin Wakeup Mask Register (Index 52h) for details about wakeup
interrupts.
ZVEN LOCK
D15
E15
D15
D15
E15
DS489PP4
BIOS-Driver Interface Control Registers (Index 6Eh, Address 0Ch - 0Dh)
ZV Port Control/Status Registers (Index 6Eh, Address 0Eh - 0Fh)
BIOS-Driver Interface Status Register (Index 7Ah)
D14
D14
D14
E14
E14
Reserved
D13
E13
D13
D13
E13
0
Event Configuration. The E[15:0] bits control the BIOS-Driver Interface mechanism.
0000h
Ph24
ZV Port Input Enable. The ZVEN bit enables the reception of asynchronous serial data on the
ZLRCLK, ZSDATA, and ZSCLK pins. The ZVEN bit routes the left and right channel data from
the ZV Port to the asynchronous SRC (ASRC) and on to the ZV volume control. This bit also func-
tions as a powerdown control for the ASRC. When this bit is ‘cleared’, the ASRC is powered
down. To use the ZV Port and the ASRC, this bit must be ‘set’.
ZV Port Locked. When ‘set’, the LOCK read-only bit indicates the ZV Port is receiving valid data
and the receiver has locked on to the data stream. If this bit is ‘cleared’, no valid data are received
on the ZV Port and the ZV input to the digital mixer will be muted.
Phase Increment. The Ph[24:0] bits contain the current Phase Increment used by the ASRC. The
current sample rate can be determined by Fs
For more information on how to use these bits see Section 7, ZV Port.
0000h
Event Status. This register, in conjunction with the BIOS-Driver Interface Control Registers (In-
dex 6Eh, Address 0Ch - 0Dh), controls the BIOS-Driver Interface mechanism.
D12
D12
D12
E12
E12
Ph23
Ph11
D11
D11
D11
E11
E11
Table 21. ZV Port Control/Status Register Index
Ph22
Ph10
D10
E10
D10
D10
E10
Register Address
Ph21
Ph9
D9
E9
D9
D9
E9
0Eh
0Fh
Ph20
Ph8
D8
D8
E8
D8
E8
ZV Port Control/Stat 1
ZV Port Control/Stat 2
Ph19
Ph7
D7
E7
D7
D7
E7
Function
Ph18
Ph6
D6
E6
D6
E6
D6
in
= Fs
Ph17
Ph5
D5
D5
E5
D5
E5
out
*Ph/16,777,216, where Fs
Ph16
Ph4
D4
E4
D4
E4
D4
Ph15
Ph3
D3
D3
E3
D3
E3
Ph14
Ph2
D2
E2
D2
E2
D2
Ph13
Ph1
D1
D1
E1
D1
E1
CS4205
out
is 48 kHz.
Ph12
Ph0
D0
D0
E0
E0
D0
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