CY7C68033-56LFXC Cypress Semiconductor Corp, CY7C68033-56LFXC Datasheet - Page 35

• Manufacturer Part Number: CY7C68033-56LFXC
• Description: IC USB NX2LP NAND CNTRLR 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68033-56LFXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• No. Of I/o's: 12
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Digital Ic Case Style: QFN
• Supply Voltage Range: 3V To 3.6V
• Core Size: 8 Bit
• Program Memory Size: 15KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PCB Layout Recommendations
Follow these recommendations
performance operation:
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Document Number: 001-04247 Rev. *H
Note
6. Source for recommendations:
At least a four-layer impedance controlled boards is
recommended to maintain signal quality.
Specify impedance targets (ask your board vendor what they
can achieve) to meet USB specifications.
To control impedance, maintain trace widths and trace spacing.
Minimize any stubs to avoid reflected signals.
Connections between the USB connector shell and signal
ground must be done near the USB connector.
Bypass/flyback caps on VBUS, near connector, are recom-
mended.
DPLUS and DMINUS trace lengths should be kept to within 2
mm of each other in length, with preferred length of 20–30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
No vias should be placed on the DPLUS or DMINUS trace
routing unless absolutely necessary.
Isolate the DPLUS and DMINUS traces from all other signal
traces as much as possible.
EZ-USB FX2™PCB Design Recommendations
[6]
to ensure reliable high
and
High Speed USB Platform Design
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the printed circuit board (PCB) is
made by soldering the leads on the bottom surface of the
package to the PCB. Therefore, special attention is required to
the heat transfer area below the package to provide a good
thermal bond to the circuit board. Design a copper (Cu) fill into
the PCB as a thermal pad under the package. Heat is transferred
from the NX2LP-Flex to the PCB through the device’s metal
paddle on the bottom side of the package. It is then conducted
from the PCB’s thermal pad to the inner ground plane by a 5 x 5
array of vias. A via is a plated through hole in the PCB with a
finished diameter of 13 mil. The QFN’s metal die paddle must be
soldered to the PCB’s thermal pad. Solder mask is placed on the
board top side over each via to resist solder flow into the via. The
mask on the top side also minimizes outgassing during the solder
reflow process.
For further information on this package design, refer to the
application note
Amkor’s Eutectic and Lead-Free CSP
Scale
information on board mounting guidelines, soldering flow, rework
process, and so on.
Packages. This application note provides detailed
Application Note for Surface Mount Assembly of
CY7C68033, CY7C68034
Guidelines.
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™ Wafer Level Chip
Page 35 of 38
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