DS2482S-800+T&R Maxim Integrated Products, DS2482S-800+T&R Datasheet - Page 12

• Manufacturer Part Number: DS2482S-800+T&R
• Description: IC MASTER I2C-1WIRE 8CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2482S-800+T&R

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 3.3 V, 5V
• Current - Supply: 750µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1-Wire Reset
1-Wire Single Bit
Bit Allocation in the Bit Byte
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
bit 7
x = don’t care
V
bit 6
x
bit 5
x
bit 4
x
B4h
None
Generates a 1-Wire Reset/Presence Detect cycle (Figure 4) at the
selected IO channel. The state of the 1-Wire line is sampled at t
and the result is reported to the host processor through the status register,
bits PPD and SD.
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2482 can process this
command.
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
t
command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Status Register (for busy polling)
1WB (set to 1 for t
PPD is updated at t
SD is updated at t
1WS, APU apply
87h
Bit Byte
Generates a single 1-Wire time slot with a bit value ‘V’ as specified by the
bit byte at the selected 1-Wire IO channel. A ‘V’ value of 0b will generate a
write-zero time slot (Figure 5), a value of 1b will generate a write one slot,
which also functions as a read data time slot (Figure 6). In either case the
logic level at the 1-Wire line is tested at t
To perform single bit writes or reads on a 1-Wire IO channel when single
bit communication is necessary (the exception).
1-Wire activity must have ended before the DS2482 can process this
command.
Command code and bit byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
t
bit (MS bit) of the bit byte.
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
bit byte.
Status Register (for busy polling and data reading)
1WB (set to 1 for t
SBR is updated at t
DIR (may change its state)
1WS, APU, SPU apply
bit 3
RSTL
SLOT
x
+ t
+ maximum 262.5ns, counted from the falling SCL edge of the first
RSTH
bit 2
x
+ maximum 262.5ns, counted from the falling SCL edge of the
bit 1
12 of 23
RSTL
RSTL
SLOT
x
RSTL
MSR
)
+ t
+ t
+ t
bit 0
RSTH
SI
x
MSP
),
,
MSR
and SBR is updated.
SI
and t
MSP