COM20022I-HT SMSC, COM20022I-HT Datasheet - Page 21

• Manufacturer Part Number: COM20022I-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1003

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
SMSC COM20022I
As an example of gating by cycle, in an ISA bus system, the Refresh period is 15μS. Continuous transfer
by DMA must be less than 15μS to prevent blocking by the Refresh cycle. A DMA cycle of consecutive
DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5μS. The Refresh
execution time is 500nS. This computes to 15μS - 2.5μS - 500nS = 12μS or 12 cycles. Therefore the
DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable-
Burst mode DMA transfer.
DMAEN bit
T
SLOW-ARB bit. T
of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.
DREQ
ARB
nWR
Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes
is the ARBITRATION Clock Period. It depends on the T
T
T
ARB
ARB
OPR
Writing Address
Pointer Low
= T
= 2 T
DATASHEET
is the period of operation clock frequency (output
OPR
OPR
minimum 4T
@ SLOW-ARB = 0
@ SLOW-ARB = 1
Page 21
ARB
OPR
and
Revision 09-27-07