LAN91C96-MU SMSC, LAN91C96-MU Datasheet - Page 37

• Manufacturer Part Number: LAN91C96-MU
• Description: IC ETHERNET CTLR MAC PHY 100TQFP
• Manufacturer: SMSC

Specifications of LAN91C96-MU

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1018

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Datasheet
Note:
SMSC LAN91C96 5v&3v
register are not accessible) is allowed. IREQ is not generated for this function and INPACK* is not
returned for accesses to the Ethernet registers.
Magic packet bit setting is ignored if the function is disabled.
8002h - Ethernet Configuration and Status Register (ECSR)
BIT 7 - Not defined
BIT 6 - Not defined
BIT 5 - IOIs8: This bit when set, indicates that the Host can only do 8 bit cycles (on D7-0). The Ethernet
function is forced in this case to eight bit mode regardless of the EN16* pin and 16BIT value. This bit also
disables (floats) the IOIs16 signal.
BIT 4 - Not defined
BIT 3 - Not defined
BIT 2 - PwrDwn: When set (1), this bit puts the LAN91C96 Ethernet function into power down mode. The
Ethernet function is also put into power down mode when the Enable Function bit (ECOR bit 0 in PCMCIA
only) is cleared. Refer to the Power Down Logic section for additional information.
BIT 1 - Intr: This bit is read/set to a one when this function is requesting interrupt service. When this bit is
set, IREQOut is asserted.
BIT 0 - Not Defined
7
0
6
0
IOIs8
5
0
DATASHEET
4
0
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3
0
Pwrdwn
2
0
Intr
1
0
0
0
Revision 1.0 (10-24-08)