CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 32

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

Table 13-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
13.0.1 ECO Trim Register
Table 13-3. ECO (ECO_TR) [0x1EB] [R/W]
Document 38-08035 Rev. *K
This read only register allows reading the current state of the Low-Voltage-Detection and Precision-Power-On-Reset compar-
ators
Bit [7:2]: Reserved
Bit 1: LVD
This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below
the trip point set by VM[2:0] (See
0 = No low-voltage-detect event
1 = A low-voltage-detect has tripped
Bit 0: PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below
the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-power-on-reset event has occurred
Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection
circuit.
Bit [7:6]: Sleep Duty Cycle [1:0]
0 0 = 1/128 periods of the Internal 32 kHz Low-speed Oscillator
0 1 = 1/512 periods of the Internal 32 kHz Low-speed Oscillator
1 0 = 1/32 periods of the Internal 32 kHz Low-speed Oscillator
1 1 = 1/8 periods of the Internal 32 kHz Low-speed Oscillator
Note This register exists in the second bank of IO space. This requires setting the XIO bit in the CPU flags register.
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
Sleep Duty Cycle [1:0]
R/W
7
–
0
7
0
R/W
Table
6
–
0
6
0
13-1)
5
–
0
5
–
0
Reserved
4
–
0
4
–
0
3
–
0
3
–
0
Reserved
CY7C63310, CY7C638xx
2
–
0
2
–
0
LVD
R
1
0
1
–
0
Page 32 of 83
PPOR
R
0
0
0
–
0
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