CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 50

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

17. Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the enCoRe II devices. The registers
associated with the interrupt controller allow disabling interrupts
globally or individually. The registers also provide a mechanism
by which a user may clear all pending and posted interrupts, or
clear individual posted or pending interrupts.
The following table lists all interrupts and the priorities that are
available in the enCoRe II devices.
Table 17-1. Interrupt Numbers, Priorities, Vectors
Document 38-08035 Rev. *K
Interrupt
Priority
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
0
1
2
3
4
5
6
7
8
9
Interrupt
Address
000Ch
001Ch
002Ch
003Ch
004Ch
005Ch
0000h
0004h
0008h
0010h
0014h
0018h
0020h
0024h
0028h
0030h
0034h
0038h
0040h
0044h
0048h
0050h
0054h
0058h
0060h
0064h
Reset
POR/LVD
INT0
SPI Transmitter Empty
SPI Receiver Full
GPIO Port 0
GPIO Port 1
INT1
EP0
EP1
EP2
USB Reset
USB Active
1 mS Interval timer
Programmable Interval Timer
Timer Capture 0
Timer Capture 1
16-bit Free Running Timer Wrap
INT2
PS2 Data Low
GPIO Port 2
GPIO Port 3
Reserved
Reserved
Reserved
Sleep Timer
Name
17.1 Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in
The interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It prevents a posted
interrupt from becoming pending.
Nested interrupts are accomplished by re-enabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
A block diagram of the enCoRe II Interrupt Controller is shown in
Figure 17-1.
on page 51.
CY7C63310, CY7C638xx
Figure 17-1.
on page 51 clocking in a ‘1’.
Page 50 of 83
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