CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 38

• Manufacturer Part Number: CY7C63833-LFXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63833-LFXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 428-2258; CY7C63833-LFXC

Table 14-9. P0.7 Configuration (P07CR) [0x0C] [R/W]
Table 14-10. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Table 14-11. P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Table 14-12. P1.2 Configuration (P12CR) [0x0F] [R/W]
Document 38-08035 Rev. *K
This register controls the operation of pin P0.7. The P0.7 pin only exists in the CY7C638(1/2/3)3.
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See
the controls in this register have any affect on the P1.0 pin.
Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high.
Bit 1: PS/2 Pull up Enable
0 = Disable the 5K ohm pull up resistors
1 = Enable 5K ohm pull up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as a PS2 style
interface.
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See
controls in this register have any affect on the P1.1 pin. When USB is disabled, the 5K ohm pull up resistor on this pin may be
enabled by the PS/2 Pull Up Enable bit of the P10CR Register
Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at V
page 68)
This register controls the operation of the P1.2.
Bit 7: CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
Note:Table 10-7, “Clock IO Config (CLKIOCR) [0x32] [R/W],”
II devices
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
CLK Output
Reserved
Reserved
Reserved
R/W
R/W
7
–
0
7
0
7
–
0
7
0
Int Enable
Int Enable
Int Enable
Int Enable
Table 21-1
Table 21-1
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
on page 58 for information on enabling the USB. When the USB is enabled, none of
on page 58 for information on enabling USB. When USB is enabled, none of the
Int Act Low
Int Act Low
Int Act Low
Int Act Low
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
TTL Threshold
TTL Thresh
on page 26 is used to select the external or internal clock in enCoRe
R/W
R/W
4
0
4
–
0
4
–
0
4
0
(Table
Reserved
14-10)
Reserved
Reserved
Reserved
3
–
0
3
–
0
3
–
0
3
–
0
OL3
Open Drain
Open Drain
Open Drain
R/W
R/W
R/W
CY7C63310, CY7C638xx
(See section
2
0
2
–
0
2
0
2
0
Pull up Enable
Pull up Enable
PS/2 Pull up
Reserved
Enable
DC Characteristics
R/W
R/W
R/W
1
0
1
0
1
–
0
1
0
Output Enable
Output Enable
Output Enable
Output Enable
Page 38 of 83
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
on
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