DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 30

• Manufacturer Part Number: DP83902AVLJ
• Description: IC CTRLR SER NETWORK IN 100PQFP
• Manufacturer: National Semiconductor

Specifications of DP83902AVLJ

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83902AVLJ

and
Bit
D0
D1
D2
D3
D4
D5
D6
D7
10 0 Internal Registers
10 3 REGISTER DESCRIPTIONS (Continued)
TRANSMIT CONFIGURATION REGISTER (TCR)
The transmit configuration establishes the actions of the transmitter section of the ST-NIC during transmission of a packet on
the network LB1 and LB0 which select loopback mode power up as 0
CRC
LB0
and
LB1
ATD
OFST
Reserved
Reserved
Reserved
Symbol
Inhibit CRC
0 CRC appended by transmitter
1 CRC inhibited by transmitter
In loopback mode CRC can be enabled or disabled to test the CRC logic
Encoded Loopback Control These encoded configuration bits set the type of loopback that is to be
performed Note that loopback in mode 2 places the ENDEC Module in loopback mode and that D3 of the
DCR must be set to zero for loopback operation
Mode 0
Mode 1
Mode 2
Mode 3
Auto Transmit Disable This bit allows another station to disable the ST-NIC’s transmitter by transmission
of a particular multicast packet The transmitter can be re-enabled by resetting this bit or by reception of a
second particular multicast packet
1 Reception of multicast address hashing to bit 62 disables transmitter reception of multicast address
hashing to bit 63 enables transmitter
Collision Offset Enable This bit modifies the backoff algorithm to allow prioritization of nodes
0 Backoff Logic implements normal algorithm
1 Forces Backoff algorithm modification to 0 to 2
standard backoff (For the first three collisions the station has higher average backoff delay making a low
priority mode )
Reserved
Reserved
Reserved
LB1
0
0
1
1
7
(Continued)
LB0
0
1
0
1
6
Normal Operation (LPBK
Internal NIC Module Loopback (LPBK
Internal ENDEC Module Loopback (LPBK
External Loopback (LPBK
5
0DH (WRITE)
OFST ATD
4
30
3
Description
min(3
LB1
e
a
2
e
n 10)
0)
0)
LB0
slot times for first three collisions then follows
1
e
CRC
0)
0
e
1)