AD9953YSVZ Analog Devices Inc, AD9953YSVZ Datasheet
AD9953YSVZ
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AD9953YSVZ Summary of contents
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FEATURES 400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/ kHz offset (DAC output) Excellent dynamic performance >80 dB SFDR @ 160 MHz (±100 kHz offset) A Serial I/O control 1.8 ...
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AD9953 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Electrical Specifications ................................................................... 4 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration ............................................................................. 7 Pin Function Descriptions .............................................................. 8 ...
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GENERAL DESCRIPTION The AD9953 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9953 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete ...
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AD9953 ELECTRICAL SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not ...
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Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low Minimum Clock Pulse Width High Maximum Clock Rise/Fall Time Minimum Data Setup Time DVDD_I/O = 3.3 V Minimum Data Setup Time DVDD_I/O = 1.8 V Minimum Data ...
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AD9953 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 43) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Input Voltage (DVDD_I/O = 1.8 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec ...
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PIN CONFIGURATION I/O UPDATE OSC/REFCLK OSC/REFCLK CRYSTAL OUT CLKMODESELECT LOOP_FILTER Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to analog ground. Note that Pin 43, DVDD_I/O, ...
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AD9953 PIN FUNCTION DESCRIPTIONS Table 3. 48-Lead TQFP/EP Pin No. Mnemonic I/O 1 I/O UPDATE DVDD I 3, 33, 42 DGND I AVDD 13, 16, 18, 19, 25, 27 14, AGND ...
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TYPICAL PERFORMANCE CHARACTERISTICS REF 0dBm ATTEN 10dB 0 PEAK 1R LOG –10 10dB/ –20 –30 –40 MARKER 100.000000MHz –70.68dB –50 – – –80 –90 –100 CENTER 100MHz #RES BW 3kHz VBW 3kHz Figure 4. ...
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AD9953 REF –4dBm ATTEN 10dB 1 0 PEAK LOG –10 10dB/ –20 –30 –40 MARKER 1.105000MHz –5.679dBm –50 – – –80 –90 ST –100 CENTER 1.105MHz #RES BW 30Hz VBW 30Hz Figure 10 ...
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Figure 16. Residual Phase Noise with F = 159.5 MHz, F OUT (Green), 4 × 100 MSPS (Red), and 20 × 20 MSPS (Blue 3.156ns 3.04ns Δ 1/Δ 1 CH1 200mVΩ M ...
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AD9953 THEORY OF OPERATION COMPONENT BLOCKS DDS Core The output frequency ( the DDS is a function of the O frequency of the system clock (SYSCLK), the value of the frequency tuning word (FTW), and the capacity of ...
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DAC Output The AD9953 incorporates an integrated 14-bit current output DAC. Unlike most DACs, this output is referenced to AVDD, not AGND. Two complementary outputs provide a combined full-scale output current (I ). Differential outputs reduce the amount of OUT ...
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AD9953 T able 5. Register Map Register Name (Serial SB) Addres s) R ange Dig ital <7:0> Power- Down Control L oad SRR <15:8> Function @ I/O UD Register No.1 Automatic (CFR1) <23:16> Sync ...
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Register Name (Serial Bit (MSB) Address) Range Bit 7 RAM Segment Control <2:0> <7:0> RAM Segment 0 Beginning Address <5:0> RAM <15:8> Segment Control <23:16> No. 0 (RSCW0) <31:24> (0x07) <39:32> RAM Segment 1 Mode ...
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Control Register Bit Descriptions Control Function Register. No. 1 (CFR1) The CFR1 is used to control the various functions, features, and modes of the AD9953. The functionality of each bit is below. CFR1<31>: RAM Enable Bit CFR1<31> (default). ...
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CFR1<9>: SDIO Input Only CFR1<9> (default). The SDIO pin has bidirectional operation (2-wire serial programm ing mode). CFR1<9> The serial data I/O pin (SDIO) is conf an input only pin (3-wire serial programming mode). CFR1<8>: LSB ...
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AD9953 CFR2<1:0>: Charge Pump Current Control Bits These bits are used to control the current setting on th pump. The default setting, CFR2 <1:0>, sets the charge pump current to the default value of 75 μA. For each 11), 25 ...
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When the RAM output drives the phase accumulator, the phase offset word (POW, Addres drives the phase-offset adder. Similarly, when the RAM out drives the phase ...
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AD9953 If the no-dwell bit is clear when the RAM equals the final address, the generator stops incrementing as the terminal frequency has been reached. The sweep is comple and does not restart until an I/O UPDATE or change in ...
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This sequence continues until the RAM address generator has incremented to an address equal to the RAM segment final address bits of the current RSCW. Upo ...
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AD9953 PROGRAMMING AD9953 FEATURES Phase Offset Control A 14-bit phase offset (θ) may be added to the output of the phase accumulator by means of the control registers. This feature provides the user with two different methods of phase con ...
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OSK Ramp Rate Timer The OSK ramp rate timer is a loadable down counter, which generates the clock signal to the 14-bit counter that generates the internal scale factor. The ramp rate timer is loaded with the value of the ...
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AD9953 External Shaped On-Off Keying Mode Operation The external shaped on-off keying mode is enabled by writing CFR1<25> Logic 1 and writing CFR1<24> Logic 0. When configured for external shaped on-off keying, the content of the ...
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SYSCLK A SYNC_CLK I/O UPDATE DATA IN DATA 1 I/O BUFFERS DATA IN DATA 0 REGISTERS THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. Synchronizing Multiple AD9953s The AD9953 allows easy synchronization of multiple AD9953s. There are three modes ...
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AD9953 There are two phases to a communication cycle with the AD9953. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9953, coincident with the first eight SCLK rising edges. The instruction byte ...
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INSTRUCTION BYTE The instruction byte contains the following information: Table 9. MSB —Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte ...
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AD9953 When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is high, the AD9953 is put into a fast recovery power-down mode. In this mode, the digital logic and the DAC digital logic are powered down. The DAC ...
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SUGGESTED APPLICATION CIRCUITS RF/IF INPUT AD9953 LPF REFCLK Figure 27. Synchronized LO for Up Conversion/Down Conversion PHASE LOOP COMPARATOR FILTER REF SIGNAL AD9953 FILTER TUNING WORLD Figure 28. Digitally Programmable Divide-by-N Function in PLL FREQUENCY MODULATED/ DEMODULATED SIGNAL REFCLK CRYSTAL ...
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... COPLANARITY VIEW A ROTATED 90 ° CCW O RDERING GUIDE Temperature M odel Range AD9953YSV −40°C to +105°C AD9953YSV-REEL7 −40°C to +105°C 1 AD9953YSVZ −40°C to +105°C 1 AD9953YSVZ-REEL7 −40°C to +105°C 1 AD9954/PCBZ RoHS Compliant Part. 1.20 9.00 MAX BSC SQ BOTTOM VIEW PIN 1 ...
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NOTES Rev Page AD9953 ...
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AD9953 NOTES ©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03374-0-5/09(A) Rev Page ...