AD9953YSVZ Analog Devices Inc, AD9953YSVZ Datasheet - Page 22

• Manufacturer Part Number: AD9953YSVZ
• Description: IC DDS DAC 14BIT 400MSPS 48-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9953YSVZ

• Resolution (bits): 14 b
• Master Fclk: 400MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Data Rate: 25Mbps
• Rf Ic Case Style: TQFP
• No. Of Pins: 48
• Supply Voltage Range: 1.71V To 1.89V, 3.135V To 3.465V
• Operating Temperature Range: -40°C To +105°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9953/PCB - BOARD EVAL FOR AD9953
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9953
PROGRAMMING AD9953 FEATURES
Phase Offset Control
A 14-bit phase offset (θ) may be added to the output of the phase
accumulator by means of the control registers. This feature
provides the user with two different methods of phase con
The first method is a static phase adjustment where a fixed
phase offset is loaded into the appropriate phase offset regis
and left unchanged. The result is that the o
b
the user to phase align the DDS out
signal, if necess
The secon
upda
mod
implement a pha
speed
rate at which pha
The AD9953
the p
automatic zeroin
contr
phase
accu
holds the value t
Con
T
when active high, holds the phase accumulator at zero for the
entire time the bit is active. When the bit goes low, inactive, the
phase accumulator is allowed to operate.
Clear and Release Function
When set, the auto-clear phase accumulator clears and releases
the phase accumulator upon receiving an I/O UPDATE. The
automatic clearing function is repeated for every subseque
I/O UPDATE until the appropriate auto-clear control bit is
cleared.
Shaped On-Off Keying
The shaped on-off keying function of the AD9953 allow
user to control the ramp-up and ramp-down time of an on
emission from the DAC. This function is used in burst
transmissions of digital data to reduce the adverse spectral
impact of short, abrupt bursts of data.
Auto and manual shaped on-off keying modes are supporte
The auto mode generates a linear scale factor at a rate
determined by the amplitude ramp rate (ARR) register
controlled by an external pin (OSK). Manual mode allows t
user to directly control the output amplitude by writing the
scale facto
T
by clearing the OSK enable bit (CFR1<25> = 0).
y a constant angle relative to the nominal signal. This allows
he continuous clear bit is simply a static control signal that,
he shaped on-off keying function may be bypassed (disabled)
mulator bit.
tinuous Cle
ifying the ph
tes the phas
hase accum
olled via th
of the I/O
d meth
r value into the amplitude scale factor (ASF) register.
allo
a .
e CFR1 bits. CFR1<13> is the automatic clear
o zero.
ry
ulator as well as a clear and release or
e offset register via the I/O
port and the frequency of SYSCLK limit the
se modulated output signal.
g function. Each feature is individually
CFR1<10> clears the phase accumulator and
se modulation can be performed.
ws for a programmable continuous zeroing o
ar Bit
od of phase control is w
ase offset as a function of time, the user can
put with some external
here the user regularly
utput signal is offset
port. By properly
However, both the
trol.
s the
nt
-off
he
ter
d.
Rev. A | Page 22 of 32
f
The modes are controlled by two bits located in th
cant byte of the control f
the shaped on-off keying enable bit. When CFR1<25> is set, th
output scaling function is enabled and CFR1<25> bypasses the
function. CFR1<24> is the internal shaped on-off keying ac
bit. When CFR1<24> is set, internal shaped on-off keying m
is active; CFR1<24> is cleared, external shaped on-off keying
mode is active. CFR1<24> is a Don’t Care if the shaped on-off
keying enable bit (CFR1<25>) is cleared. The power-up
condition is shaped on-off keying disabled (CFR1<25> = 0).
Figure 20 shows the block diagram of the OSK circuitry.
AUTO Shaped On-
The auto shaped on-off keying mode is active when CFR1<25>
and CFR1<24> are set. When auto shaped on-off keying mode
is enabled, a single scale factor is internally generated and
applied to the multiplier input for scaling the output of the DDS
core block (see Figure 20). The scale factor is the output of a
14-bit counter that increments/decrements at a rate de
by the contents of the 8-bit output ramp rate register. The scale
factor increases if the OSK pin is high and decreases if t
pin is low. The scale factor is an unsigned value such that
multiply the DDS core output by 0 (decimal) and 0x3FFF
multiplies t
For those users who use the full amplitude (14 bits) but need
fast ramp rates, the inter
is controlled via the ASF
increment/decrement step size of the internally generated scal
factor per the ASF<15:14> bits.
A special feature of this mode is that the maximum output
amplitude allowed is limited by the conten
scale factor register. This allows t
than full scale.
Table 8. Auto-Scale Factor Internal Step Size
ASF<15:14> (Binary)
00
01
10
11
he DDS core output by 16383 (decimal).
Off Keying Mode Operation
unction register (CFR). CFR1<25> is
nally generated scale factor step size
<15:14> bits. Table 8 describes the
Increment/Decrement Size
1
2
4
8
he user to ramp to a value less
ts of the amplitude
e most signifi-
termined
he OSK
all 0s
tive
ode
e
e