DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 207

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: See
Bit 7: TFDL Register Select (TFDLS)
Bit 6: Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the
SLC-96 alignment pattern and data from the T1TSLC1–3 registers. See Section
Bit 5: Transmit DDS Zero Suppression Enable (TDDSEN)
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode)
or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft
(D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of
synchronization.
Bit 2: Transmit RAI Select (TRAIS)
Note: This bit only selects the type of remote alarm to send. To enable transmission of remote alarm, set
TCR1.TRAI.
Bit 0: Transmit-Side Bit 7 Zero Suppression Enable (TB7ZS)
0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (T1.TCR2.6).
1 = Source FDL or Fs bits from the internal HDLC controller.
0 = SLC-96 insertion disabled.
1 = SLC-96 insertion enabled.
0 = No DDS stuffing.
1 = DDS stuffing enabled. Force zero code 10011000 in all zero byte channels based on the channel
select registers TDDS1–3.
0 = Transmit RAI is T1.
1 = Transmit RAI is J1.
0 = No stuffing occurs.
1 = Force bit 7 to a one as determined by the GB7S bit at TCR1.3.
E1.TCR2
TFDLS
7
0
D4—Zeros in bit 2 of all channels.
ESF—00FF pattern in the FDL.
D4—A one in the S-bit position of frame 12.
ESF—All ones in FDL.
for E1 Mode.
TSLC96
T1.TCR2 (T1 Mode)
Transmit Control Register 2
182h + (200h x (n - 1)) : where n = 1 to 8
6
0
TDDSEN
5
0
FBCT2
207 of 286
4
0
FBCT1
3
0
DS26518 8-Port T1/E1/J1 Transceiver
TRAIS
9.9.4.3
2
0
for details.
—
1
0
TB7ZS
0
0