DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 47

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26518 8-Port T1/E1/J1 Transceiver
9.8.4 Transmit and Receive Channel Blocking Registers
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLKn and TCHBLKn pins, respectively. The RCHBLKn
and TCHBLKn pins are user-programmable outputs that can be forced either high or low during individual
channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications.
When the appropriate bits are set to a one, the RCHBLKn and TCHBLKn pins will be held high during the entire
corresponding channel time. When used with a T1 (1.544MHz) backplane, only TCBR1 to TCBR3 will be used.
TCBR4 is included to support an E1 (2.048MHz) backplane when the elastic store is configured for T1-to-E1 rate
conversion (See Section 9.8.1).
9.8.5 Transmit Fractional Support (Gapped Clock Mode)
The DS26518 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled
via the Transmit Gapped Clock Channel Select Registers (TGCCS1–4). The transmit path is enabled for gapped
clock mode with the TGCLKEN bit (TESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by TESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
9.8.6 Receive Fractional Support (Gapped Clock Mode)
The DS26518 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLKn signal. The channel selection is
controlled via the Receive Gapped Clock Channel Select Registers (RGCCS1–4). The receive path is enabled for
gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56kbps and 64kbps channel formats are supported as
determined by RESCR.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
channel is omitted (only the seven most significant bits of the channel have clocks).
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