DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 217

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8
bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or
BOC controller circuits.
Bit 3: Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the
TMEND bit set. An abort is automatically sent.
Bit 2: Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a
message.
Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO
empties beyond the low watermark as defined by the transmit low watermark bits (TLWM), rising edge detect of
TLWM.
Bit 0: Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty
byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: Some bits in this register are latched and can create interrupts.
Bit 1: Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync
pattern in the incoming data stream.
Bit 0: Loss Of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is
searching for the sync pattern in the incoming data stream.
—
—
—
7
0
7
0
TLS2
Transmit Latched Status Register 2 (HDLC)
191h + (200h x (n - 1)) : where n = 1 to 8
TLS3
Transmit Latched Status Register 3 (Synchronizer)
192h + (200h x (n - 1)) : where n = 1 to 8
—
—
—
6
0
6
0
—
—
—
5
0
5
0
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TFDLE
—
—
4
0
4
0
TUDR
TUDR
—
3
0
3
0
DS26518 8-Port T1/E1/J1 Transceiver
TMEND
TMEND
—
2
0
2
0
TLWMS
TLWMS
LOF
1
0
1
0
LOFD
TNFS
TNFS
0
0
0
0