PIC16F77-I/P Microchip Technology Inc., PIC16F77-I/P Datasheet - Page 138

• Manufacturer Part Number: PIC16F77-I/P
• Description: 40 PDIP .600in TUBE, 14 KB Flash, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F77-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16F7X
TABLE 15-9:
DS30325B-page 136
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
Param.
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
*
2: A Fast mode (400 kHz) I
These parameters are characterized but not tested.
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
requirement T
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line T
Standard mode I
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
:
:
:
:
:
STA
DAT
STO
STA
DAT
I
2
C BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition
hold time
Data input hold time 100 kHz mode
Data input setup
time
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
:
2
DAT
C bus specification), before the SCL line is released.
≥ 250 ns must then be met. This will automatically be the case if the device does not
Characteristic
2
C bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max. + T
20 + 0.1C
20 + 0.1C
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
SU
CY
CY
:
DAT
B
B
= 1000 + 250 = 1250 ns (according to the
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
pF
µs
µs
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
 2002 Microchip Technology Inc.
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10 - 400 pF
C
10 - 400 pF
Only relevant for
Repeated START
condition
After this period the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
2
is specified to be from
is specified to be from
C bus system, but the
Conditions