PIC16F77-I/P Microchip Technology Inc., PIC16F77-I/P Datasheet - Page 97

• Manufacturer Part Number: PIC16F77-I/P
• Description: 40 PDIP .600in TUBE, 14 KB Flash, 368 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F77-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 33
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

12.10 Power Control/Status Register
The Power Control/Status Register, PCON, has two
bits to indicate the type of RESET that last occurred.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see
TABLE 12-3:
TABLE 12-4:
TABLE 12-5:
 2002 Microchip Technology Inc.
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(PCON<1>)
Oscillator Configuration
POR
0
0
0
1
1
1
1
1
XT, HS, LP
(PCON)
(0004h).
RC
(PCON<0>)
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
BOR
x
x
x
0
1
1
1
1
Condition
(STATUS<4>)
72 ms + 1024 T
PWRTE = 0
TO
1
0
x
1
0
0
u
1
72 ms
Power-up
(STATUS<3>)
OSC
PD
1
x
0
1
1
0
u
0
PWRTE = 1
1024 T
Program
PC + 1
Counter
PC + 1
000h
000h
000h
000h
000h
—
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from
SLEEP
OSC
if bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
(1)
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
72 ms + 1024 T
Register
STATUS
Brown-out
72 ms
Significance
OSC
PIC16F7X
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
Register
Wake-up from
DS30325B-page 95
PCON
1024 T
SLEEP
—
OSC