ICS1893YI-10LF IDT, Integrated Device Technology Inc, ICS1893YI-10LF Datasheet - Page 73

• Manufacturer Part Number: ICS1893YI-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893YI-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1893YI-10LF

7.3.11 Link Status (bit 1.2)
7.3.12 Jabber Detect (bit 1.1)
7.3.13 Extended Capability (bit 1.0)
ICS1893Y-10 Rev F 1/20/04
The purpose of this bit 1.2 (which is also accessible through the QuickPoll Detailed Status Register, bit
17.0) is to determine if an established link is dropped, even momentarily. To indicate a link that is:
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This bit is a latching low (LL) bit that the Link Monitor function controls. (For more information on latching
high and latching low bits, see
Bits”.) The Link Monitor function continually observes the data received by either its 10Base-T or
100Base-TX Twisted-Pair Receivers to determine the link status and stores the results in the Link Status
bit.
The criterion the Link Monitor uses to determine if a link is valid or invalid depends on the following:
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For more information on the Link Monitor Function (relative to the Link Status bit), see
“10Base-T Operation: Link
The purpose of this bit is to allow an STA to determine if the ICS1893Y-10 detects a Jabber condition as
defined in the ISO/IEC specification.The ICS1893Y-10 Jabber Detection function is controlled by the
Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the
ICS1893Y-10 Jabber Detection function must be enabled. When bit 18.5 is logic:
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•
Note:
1. The Jabber Detect bit is accessible through both the Status register (as bit 1.1) and the QuickPoll
2. The Jabber Detect bit is a latching high (LH) bit. (For more information on latching high and latching low
The STA reads bit 1.0 to determine if the ICS1893Y-10 has an extended register set. In the ICS1893Y-10
this bit is always logic one, indicating that it has extended registers.
Valid, the ICS1893Y-10 sets bit 1.2 to logic one.
Invalid, the ICS1893Y-10 clears bit 1.2 to logic zero.
Type of link
Present link state (valid or invalid)
Presence of any link errors
Auto-negotiation process
Zero, the ICS1893Y-10 disables Jabber Detection and sets the Jabber Detect bit to logic zero.
One, the ICS1893Y-10 enables Jabber Detection and sets the Jabber Detect bit to logic one upon
detection of a Jabber condition. When no Jabber condition is detected, the Jabber Detect bit is not
altered.
ICS1893Y-10 - Release
Detailed Status Register (as bit 17.2). A read of either register clears the Jabber Detect bit.
bits, see
Section 7.1.4.1, “Latching High Bits”
Monitor”.
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 7.1.4.1, “Latching High Bits”
All rights reserved.
73
and
Section 7.1.4.2, “Latching Low
and
Chapter 7 Management Register Set
Section 7.1.4.2, “Latching Low
Bits”.)
Section 6.5.5,
January, 2004