ispPAC-POWR607-01N32I Lattice, ispPAC-POWR607-01N32I Datasheet - Page 22

• Manufacturer Part Number: ispPAC-POWR607-01N32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I
• Manufacturer: Lattice

Specifications of ispPAC-POWR607-01N32I

• Number Of Voltages Monitored: 6
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 300 us
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.64 V
• Supply Current (typ): 3.5 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 4-5. ispPAC-POWR607 TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR607. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR607 has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 4-5.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR607 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification com-
patibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR607 and leaves it in its
functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
device type and version code (Figure 4-19). Access to the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for
this instruction is defined by Lattice as shown in Table 4-5.
BULK_ERASE
BYPASS
DISCHARGE
ERASE_DONE_BIT
EXTEST
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DONE_BIT
PROGRAM_ENABLE
PROGRAM_SECURITY
RESET
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_INIT_ADDR_FOR_PROG_INCR
PLD_PROG_INCR
PLD_PROGRAM
PLD_VERIFY
PLD_VERIFY_INCR
UES_PROGRAM
UES_READ
Instruction
Command
0000 0011
1111 1111
0001 0100
0010 0100
0000 0000
0001 0110
0001 1000
0001 1110
0010 1111
0001 0101
0000 1001
0010 0010
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
00011100
Code
Bulk erase device
Bypass - connect TDO to TDI
Fast VPP discharge
Erases ‘Done’ bit only
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, including FET driver outputs
Sample/Preload. Default to bypass.
Disable program mode
Programs the Done bit
Enable program mode
Program security fuse
Resets device
PLD_Address register (61 bits)
PLD_Data register (81 bits)
Initialize the address register for auto increment
Program column register to E
Program PLD data register to E
Verifies PLD column data
Load column register from E
Program UES bits into E
Read contents of UES register from E
4-22
2
ispPAC-POWR607 Data Sheet
2
Comments
2
and auto increment address register
and auto increment address register
2
2
(32 bits)