PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 19

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Figure 8. Typical LXT310 Hardware Mode Application
NOTE: The LXT310 is
LXP600A
FRAMER
See Note 1
compatible with a wide
variety of framing/
signaling devices.
T1/ESF
CLAD
selecting the 22.5 dB LBO, and the EGL pin is tied low, allowing for full receiver gain. The
TAOS, LLOOP and RLOOP diagnostic modes are individually controllable. The RCLK input to
the OR gate at RLOOP allows for clocking of the RLOOP pin, which enables network loopback
detection. The receive and transmit line interfaces are identical to the Host mode application
shown in
CLKO
CLKI
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
FSI
Figure
1.544
MHz
6.176
MHz
7.
2.048 MHz
MCLK
TCLK
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
JASEL
LOS
TTIP
TGND
TRANSCEIVER
1.0 F
LXT310
RLOOP
NLOOP
LLOOP
T1 CSU/ISDN PRI Transceiver — LXT310
RRING
TRING
RGND
TAOS
68 F
LBO1
LBO2
LATN
RTIP
RV+
EGL
TV+
0V
100
0.1 F
12.5
12.5
V+
1:1
1:2
From
CMOS
Control
Logic
T1 Line
Receive
1.544 MHz
T1 Line
Transmit
19