PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 21

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Recommended output load at TTIP and TRING
AMI Output Pulse Amplitudes
Jitter added by the transmitter
Receive signal attenuation
Allowable consecutive zeros before LOS
Input jitter tolerance
Jitter attenuation curve corner frequency
range @ 772 kHz
1. Typical values are measured at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal to TCLK is jitter-free.
3. Guaranteed by characterization; not subject to production testing.
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Table 10. Analog Characteristics (Under Recommended Operating Conditions)
Figure 9. 1.544 Mbps DS1 Pulse Mask (T1.403 - 1995)
Table 11. Pulse Mask Corner Point Specifications
Time (ns)
250
325
325
0
Parameter
Maximum Curve
-0.5
1.5
1.0
0.5
0.0
2
-1
10 Hz - 8 kHz
8 kHz - 40 kHz
10 Hz - 40 kHz
Broad Band
Mode 1 (EGL = 1)
Mode 2 (EGL = 0)
10 kHz - 100 kHz
1 Hz
Normalized
Amplitude
3
(In Unit Intervals)
-0.5
% V
120
80
5
5
Time
Min
160
138
2.4
0.4
50
–
–
–
–
0
0
–
0.5
Typ
175
3.0
26
36
–
–
–
–
–
–
–
3
T1 CSU/ISDN PRI Transceiver — LXT310
1
Time (ns)
350
350
400
0
1.0
Max
0.02
0.02
0.02
0.04
200
190
3.6
–
–
–
–
–
Minimum Curve
Units
dB
dB
Hz
1.5
UI
UI
UI
UI
UI
UI
V
–
measured at the output
with LBO1 = 0, and
LBO2 = 0
Test Conditions
% V
50
90
-5
-5
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