PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet
PEB24902HV2.1XT
Specifications of PEB24902HV2.1XT
Related parts for PEB24902HV2.1XT
PEB24902HV2.1XT Summary of contents
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IEC-4-AFE ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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IEC-4-AFE-X Revision History: Previous Version: Page Subjects (major changes since last revision) Page 9 Aplication: Added reference to System Description GEMINAX MAX Page 10 References: Updated Page 13 Added N.C.: Not connected. Page 28 Removed Figure 7 (PSD mask for ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5 External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Serial Control Interface (SCI ...
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IEC-4-AFE-X Quad ISDN Echocancellation Circuit Analog Front End for Splitterless ADSL over ISDN IEC-4-AFE-X Version 3.2 Features 1 Overview The IEC-4-AFE-X Version 3.2 is part of Infineon´s chip set for a splitterless, FDD (non-overlapped) ADSL over ISDN linecard based on ...
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Application Diagram Figure 1 shows a typical application of IEC-4-AFE-X Version 3.2 together with Infineon´s IC family for splitterless FDD ADSL over ISDN and DFE-T/Q Version V2.2 for an integrated voice and data solution (IVD). External ADSL Circuitry Starpoint ...
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... Related Documentation 1. AFE V2.1, Quad ISDN Echocancellation Circuit Analog Front End, PEF / PEB 24902 Version 2.1, Data Sheet DS2, Infineon Technologies AG, January 2001 2. TS 102080 V1.3.2, Transmission and Multiplexing; ISDN basic rate access, Digital transmission system on metallic local lines, ETSI, May 2000 3. TS 102080 V1.4.1, Transmission and Multiplexing ...
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External Signals Attention: Any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective Data Sheet. In case the chips are used incorrectly or not used within ...
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Pin Diagram GND 49 a2 XDN2 REF2 AIN2 52 BIN2 53 54 DOUT TDI 55 TDO 56 TCK 57 TMS ...
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General Aspects The following abbreviations are used: I Input. Digital LvTTL levels O Output. Digital LvTTL levels OD Open Drain PU Pull Up PD Pull Down N.C. Not Connected 2.3.2 Pin Description: Changes to AFE V2.1 Some unused pins ...
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Table 2 Address Pins and Test Mode (cont’d) Pin Old New No. 4 N.C. TEST 1 N.C. res. 48 N.C. res. 2.3.3 Pin Description: Complete List Table 3 Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) Power ...
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Table 3 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output ( N.C. REF1 51 V N.C. REF2 62 V N.C. REF3 JTAG Boundary Scan 57 TCK I 58 TMS I (PU) 55 TDI I (PU) ...
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Table 3 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 16 AOUT1 O 13 BOUT1 O 52 AIN2 I 53 BIN2 I 47 AOUT2 O 44 BOUT2 O 61 AIN3 I 60 BIN3 I 2 AOUT3 ...
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Table 3 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 40 PDM2 O 8 PDM3 O 31 XDN0 N.C. 18 XDN1 N.C. 50 XDN2 N.C. 63 XDN3 N.C. 24 SDX I 41 SDR O 23 CODE ...
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Table 3 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 26 CLOCK I 22 PLLF I (PU) Serial Control Interface 12 SCS I (PD) 43 SCLK I (PD) 27 DIN I (PD) 54 DOUT OD Address ...
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Functional Description Attention: Any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective Data Sheet. In case the chips are used incorrectly or not used within ...
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Block Diagram SCI Bus Serial Control Interface ADDR2-0 DFE Digital Interface Interface JTAG Boundary Scan, Interface TAP Control Figure 4 Block Diagram Data Sheet Fuse Digital Noise DAC Filter Shaper ADC PREFI AGC Level Detect 20 PEB 24902 PEF ...
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Clock Generation All timing signals are derived from a 15.36 MHz system clock. The 15.36 MHz clock can be provided by the IEC-4-AFE-X Version 3 crystal based PLL, which is synchronized to either an 8 kHz or ...
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H1 j H1max 0.01 0.01 Figure 5 Jitter Transfer Gain H1e 0.01 0.01 Figure 6 Maximum Phase Difference Due to Sinusoidal ...
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Access Network. PLLF tied to high or left open results in a higher resonance frequency for accelerated synchronization. The PLLF pin has an internal pull-up resistor. The PLL automatically determines whether the frequency at pin CLOCK is 8 kHz or ...
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Table 4 PLL Characteristics (cont’d) Parameter Output current at XOUT during start-up Output current at XOUT after synchronization Table 5 PLL Input Requirements Parameter Accuracy of the reference at CLOCK to enable synchronization Peak-to peak Jitter of the CLOCK signal ...
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Table 6 Specification of the Crystal (cont’d) Parameter Operating frequency Load Load Current Load capacitance Overall tolerance f/f Resonance resistance R r Shunt capacitance C 0 Motional capacitance C 1 Overall pullability ...
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Analog-to-Digital Converter A first order low-pass anti alias filter is provided at the input of the ADC. The ADC is a sigma-delta modulator of second order using a clock rate of 15.36 MHz. During normal operation the ADC evaluates ...
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Table 7 Specified Data of the Analog-to-Digital Converter (cont’d) Parameter Signal/(Noise + Distortion) (sine wave 4 Vpp between AINx/ BINx) Signal/(Noise + Distortion) (sine wave 4.6 Vpp between AINx/BINx) DC offset voltage DC offset voltage ADC gain ADC gain Attenuation ...
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Digital Low-Pass Filter The IEC-4-AFE-X Version 3.2 implements a digital low-pass filter. The filter characteristic is optimized for high stop-band attenuation with a very steep transition from pass-band to stop-band. Due to this filter characteristic and in connection with ...
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Table 9 Characteristics of the TX-Path Parameter Symbol Signal / Noise S/N Signal / (Noise and S/D Distortion) Common mode DC level Offset between AOUTx and BOUTx ratio between 1 and 3 symbols Variation of the signal amplitude measured over ...
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Analog Loop-Back Function The loop-back bit (LOOP) set to ONE on SDX activates an internal analog loop-back. This loop-back is closed near the U interface. Signals received on AINx / BINx will neither be evaluated nor recognized by the ...
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Table 10 Specified Data of the Level Detection Circuit Parameter Cut-off frequency of the input filter Threshold of level detect (2B1Q) Threshold of level detect (4B3T) DC level of level detect (common mode level) 3.4 Digital Interface On the digital ...
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SY: First bit of the time slots with transmission data. For synchronization and bit allocation on SDX and SDR set to ONE. "0": Reserved bit. Reserved bits are currently not defined and shall be set to ZERO. Some ...
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Figure 9 Frame Structure on SDX and SDR in 4B3T Mode The 4B3T data is coded with the bits TD1, TD0: Table 12 Coding of the 4B3T Data Pulse (AOUTx/BOUTx) 4B3T Data Pulse – 1 3.4.3 Propagation ...
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ADDR2 AFE-X V3.2 ADDR1 (4-ch.) ADDR0 ADDR2 ADDR1 AFE-X V3.2 (4-ch.) ADDR0 GEMINAX-A0 GEMINAX-A0 MAX MAX Figure 10 SCI Bus The SCI bus connects all those IEC-4-AFE-X Version 3.2 and GEMINAX MAX devices, whose lineports are connected to common twisted ...
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Boundary Scan Test Controller The IEC-4-AFE-X Version 3.2 provides a boundary scan support for a cost effective board testing. It consists of: • Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1 specification. • Test access ...
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Table 14 Sequence of Pins in the Boundary Scan (cont’d) Boundary Scan Pin Number Number TDI ––> TAP Controller The Test Access Port (TAP) controller implements the state ...
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SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both activities are transparent to the system functionality. IDCODE Register The 32-bit ...
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Operational Description Attention: Any warranty, whether express or implied shall be subject to the use of the chips within the procedure as outlined in the respective Data Sheet. In case the chips are used incorrectly or not used within ...
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Figure 11 Power-on-Reset Behavior of the IEC-4-AFE-X after V Table 16 Parameters for POR Activation Parameter Maximum V slope (rising or falling) DD POR enable threshold V below 1V-time DD 4.3 Power Down Transmit path, ...
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The digital interface, the PLL, and the level detection are not affected by the power down. The SCI is fully functional, when SCS = 1 (independently on the power down function of any channel). 4.4 Power Consumption All measurements with ...
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External Circuitry External circuitry meets electrical characteristic requirements of from Infineon´s recommendations for external circuitry may significantly degrade either ISDN and / or ADSL performance. Attention: Any warranty, whether express or implied shall be subject to the use of ...
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Note: 1. The purpose of this model impedance is for splitter specification not a requirement on the input impedance of the ADSL transceiver. 2. Z_ADSL-I does not include the blocking capacitors C hybrid (see Figure 13). 5.3 Starpoint ...
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The distances between Starpoint - AFE-X (Lat) and Starpoint - GEMINAX MAX (Laa) shall not exceed the order of magnitude of typical linecard dimensions. Note: For testing purposes (for instance PSD measurement), it may be desirable to measure using ETSI´s ...
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Table 21 External Circuitry Parameters - 4B3T ADSL-friendly (cont’d) Parameter Coupling capacitance between the windings on the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on ...
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Table 22 External Circuitry Parameters -2B1Q ADSL-friendly Parameter U-Transformer EP13 for 2B1Q TRTEP13S-U255C013 Rev2 U-Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side L Coupling capacitance ...
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Electrical Characteristics 6.1 Absolute Maximum Ratings Table 23 Absolute Maximum Ratings Parameter Max. storage and transportation temperature Max. junction temperature Supply voltage Voltage on any pin Voltage between GNDx to any other GNDx Voltage between VDDx to any other ...
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Figure 16 Maximum Line Input Current 6.2 Operating Ambient Temperature The operating ambient temperature for standard and extended temperature versions shall be in the limits as follows: Operating Ambient Temperature Table 24 Version PEB 24902 PEF 24902 6.3 Supply Voltages ...
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The following blocking circuitry is suggested VDD a0 VDD a1 VDD a2 VDD a3 VDD d1 VDD d2 1) 100nF GND d2 GND d1 GND a3 GND a2 GND a1 GND a0 1) These capacitors should be located as near ...
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Table 25 DC Characteristics (cont’d) Parameter Symbol High level input I IH leakage current High level output V OH voltage (Pin CL15, Pin DOUT) High level output V OH voltage (all other outputs) Low level output V OL voltage Input ...
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Boundary Scan Timing TCK TMS TDI TDO Figure 18 Boundary Scan Timing Table 27 Boundary Scan Timing Parameter test clock period test clock period low test clock period high TMS set-up time to TCK TMS hold time from TCK ...
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Package Outlines Figure 19 P-MQFP-64-9 HS (Plastic Metric Quad Flat Package) • K/W (FEA, PCB 2s2p, T th_ja Note: This K/W is calculated for a JEDEC test board (2s2p). The R th_ja customer ...
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