PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet - Page 22

PEB24902HV2.1XT

Manufacturer Part Number
PEB24902HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB24902HV2.1XT

Number Of Line Interfaces
1
Lead Free Status / Rohs Status
Compliant
Figure 5
Figure 6
If the input signal at pin CLOCK disappears being stuck to high or low, the PLL continues
to generate the CL15 clock. In this case the PLL keeps the last setting. The accuracy of
the frequency of CL15 degenerates in the long term only due to changes in temperature
and ageing.
The resonance frequency can be set to two different values using the pin PLLF. PLLF
tied to low sets the PLL to a low resonance frequency suited for applications in the
Data Sheet
H1e
H1
H1max
20
80
j
j
10
40
20
20
40
60
80
0
Jitter Transfer Gain in dB
Maximum Phase Difference Due to Sinusoidal Input Jitter
10
0.01
10
20
30
40
0.01
0
0.01
0.01
0.1
0.1
1
1
22
fn
f
j
fn
f
j
10
10
Functional Description
100
100
Rev. 1, 2004-05-28
PEB 24902
PEF 24902
1000
1000
1000
1000

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