PEB24902HV2.1XT Infineon Technologies, PEB24902HV2.1XT Datasheet - Page 18

PEB24902HV2.1XT

Manufacturer Part Number
PEB24902HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB24902HV2.1XT

Number Of Line Interfaces
1
Lead Free Status / Rohs Status
Compliant
Table 3
Pin No. Symbol
26
22
Serial Control Interface
12
43
27
54
Address Pins and Test Mode
35
14
45
4
1
48
1)
Data Sheet
Only four lines are supported
CLOCK
PLLF
SCS
SCLK
DIN
DOUT
ADDR0
ADDR1
ADDR2
TEST
res.
res.
Pin Definitions and Functions (cont’d)
Input (I)
Output (O)
I
I (PU)
I (PD)
I (PD)
I (PD)
OD
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
Description
Clock
8 kHz or 2048 kHz clock as a time base of the
15.36 MHz clock. Connect to GND if not used.
PLL Frequency
Select corner frequency of PLL Jitter Transfer
function. Internal pullup resistor (I
(typ.)).
Tie to ’1’
Serial Clock
Clock signal of the SCI
Serial Data Receive
Receive data line of the SCI
Serial Data Transmit
Transmit data line of the SCI
Address 0
Pinstrapping of AFE-X address for SCI access
Address 1
Pinstrapping of AFE-X address for SCI access
Address 2
Pinstrapping of AFE-X address for SCI access
TEST
0:
1:
Note: Pin TEST must be kept low.
Reserved
Reserved for future use. Leave open.
Reserved
Reserved for future use. Leave open.
Inactive
IEC-4-AFE-X Version 3.2 test mode
18
PLLF
External Signals
Rev. 1, 2004-05-28
= -100 A
PEB 24902
PEF 24902

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