PSB21383H-V13TR Infineon Technologies, PSB21383H-V13TR Datasheet - Page 197

• Manufacturer Part Number: PSB21383H-V13TR
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13TR

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFBS
RFBS
Bit6
0
0
1
1
Note: A change of RFBS will take effect after a receiver command (CMDR.RMC,
SRA
0: Receive Address is not stored in the RFIFO
1: Receive Address is stored in the RFIFO
XCRC
0: CRC is transmitted
1: CRC is not transmitted
RCRC
0: CRC is not stored in the RFIFO
1: CRC is stored in the RFIFO
ITF
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0: Idle (continuous ’1’)
1: Flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
Data Sheet
CMDR.RRES,) has been written
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the line interface can not be accessed
RFBS
Bit5
0
1
0
1
… Receive FIFO Block Size
… Store Receive Address
… Transmit CRC
… Receive CRC
… Interframe Time Fill
Block Size
Receive FIFO
32 byte
16 byte
8 byte
4 byte
187
Detailed Register Description
PSB 21381/2
PSB 21383/4
2001-03-12