PSB21383H-V13TR Infineon Technologies, PSB21383H-V13TR Datasheet - Page 227

• Manufacturer Part Number: PSB21383H-V13TR
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13TR

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.3.11
Value after reset: 00
STI
For all interrupts in the STI register following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
STOVxy
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
Data Sheet
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
STI - Synchronous Transfer Interrupt
STOV
7
21
... Synchronous Transfer Overflow Interrupt
... Synchronous Transfer Interrupt
STOV
H
20
STOV
11
STOV
10
217
STI
21
STI
20
Detailed Register Description
STI
11
0
STI
10
PSB 21381/2
PSB 21383/4
2001-03-12
RD (58
H
)