PSB21383HV13XP Infineon Technologies, PSB21383HV13XP Datasheet - Page 217

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PSB21383HV13XP

Manufacturer Part Number
PSB21383HV13XP
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21383HV13XP

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
.RSS2, RSS1
The reset sources and the SDS2 functionality for the RSTO/SDS2 output pin can be
selected according to the table below.
For RSS = ’00’ no reset is generated at pin RSTO/SDS2.
For RSS = ’01’ a serial data strobe is output at pin RSTO/SDS2 (see chapter 2.2.3).
For RSS = ’10’ an External Awake or a change in the downstream C/I0 channel
For RSS = ’11’ the watchdog function is enabled (see chapter 6.1).
A hardware reset is always output at pin RSTO/SDS2.
After a reset pulse and the corresponding interrupt (WOV or CIC) have been generated
by the SCOUT the actual reset source can be read from the ISTA.
Data Sheet
RSS2
Bit 1
0
0
1
1
RSS1
Bit 0
0
1
0
1
... Reset Source Selection 2,1
generates a reset of 125 µs
(see chapter 6.1).
C/I Code
Change
--
--
--
x
EAW
--
--
--
x
207
Watchdog
t
Timer
--
--
--
x
250 µs pulse length at the pin RSTO
Detailed Register Description
Functionality
SDS2
--
--
--
x
PSB 21381/2
PSB 21383/4
2001-03-12

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