PSB21383HV13XP Infineon Technologies, PSB21383HV13XP Datasheet - Page 86

• Manufacturer Part Number: PSB21383HV13XP
• Manufacturer: Infineon Technologies

Specifications of PSB21383HV13XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
2.3.5
The S/T transmitter is shifted by two S/T bits - 7 oscillator periods (plus analog delay plus
delay of the external circuitry) with respect to the received frame. To compensate
additional delay introduced into the receive and transmit path by the external circuit the
delay of the transmit data can be reduced by another two oscillator periods (260 ns).
Therefore PDS of the TR_CONF2 register must be programmed to ’1’. This delay
compensation might be necessary in order to comply with the "total phase deviation input
to output" requirement of ITU-T recommendation I.430 which specifies a phase deviation
in the range of – 7% to + 15% of a bit period.
2.3.6
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM interface. In all other states ’1’s are transmitted to
the IOM interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 47 shows the data delay between the IOM and the S/T interface and vise versa.
For the D channel the delay from the IOM to the S/T interface is only valid if S/G
evaluation is disabled (see chapter 2.2.7.2).
Figure 47
Data Delay between IOM and S/T Interface
NT -> TE
TE -> NT
FSC
DU
DD
B1
B1
Phase Deviation
Data Transfer and Delay between IOM and S/T Interface
F
B2 D
B2 D
F
B1
B1
E
D
D
E
B2
B2
E
B1
B1
B2 D
B2 D
D
D
B1
B1
E
D
D
E
B2
B2
E
B1
B1
76
B2 D
B2 D
D
F
D
F
B1
B1
E
D
E
D
B2
B1
B1
B2
E
B2 D
B2 D
D
D
B1
B1
E
E
D
PSB 21381/2
PSB 21383/4
D
B2
B2
E
Interfaces
2001-03-12
line_iom_s.vsd
D
D