Z8623012PSG Zilog, Z8623012PSG Datasheet - Page 15

• Manufacturer Part Number: Z8623012PSG
• Description: IC SMART V-CHIP W/2ND I2C 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8623x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CMOS
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

T
PS000401-TVC0699
Symbol
LPF
RREF
V
V
PB
SDA
SCLK
NC
INTRO
NC
ABLE
SS
DD
(A)
1. P
IN
Pin #
9
10
11
12
13
14
15
16
17
18
D
ESCRIPTIONS
Function
Loop Filter
Resistor Reference
Power Supply
(Anlalog) GND
Power Supply +5V
Program Blocking
Serial Data
Serial Clock
No Connect
Interrupt Output
No Connect
B
LOCK
D
IAGRAM AND
Z86230—PRELIMINARY
O
Direction
Output
Input
N/A
N/A
Output
In/Output This pin is the bidirectional data line for
Input
N/A
Output
N/A
PERATIONAL
O
Description
Loop Filter. A series RC low-pass filter must be
tied between this pin and analog ground
V
from the pin to V
Reference setting resistor. This resistor must
be 10 kOhms, ±2%.
This pin is the lowest potential power pin for
the analog circuit that is typically tied to
system ground.
The voltage on this pin is nominally 5.0 Volts,
and may range between 4.75 to 5.25 Volts with
respect to the V
This pin is HIGH(1) when the received Content
Advisory packet matches the viewers
selection as entered into the Content Advisory
Rating Select registers.
sending and receiving serial data.
This pin acts as an input pin for the serial clock
signal from the I
expected to be within I
No Connect
This pin provides an interrupt signal to the
master control device in accordance with the
settings in the Interrupt Mask Register.
No Connect
VERVIEW
SS
(A). There must also be second capacitor
C7
C6
SS
2
SS
C master. The clock rate is
pins.
(A).
R5
C5
2
C limits.
9
8
LPF
CSYNC
P
IN
D
ESCRIPTIONS
15