Z8623012PSG Zilog, Z8623012PSG Datasheet - Page 20

• Manufacturer Part Number: Z8623012PSG
• Description: IC SMART V-CHIP W/2ND I2C 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8623x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CMOS
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

4.1.4 Reading Data Using the I
T
20
RBS
Command
Bank 0
Bank 1
Bank 2
Bank 3
N
is calculated such that the addition of the 32 data bytes and the checksum modulo 256 equals zero. The
checksum should always be evaluated after reading this data to ensure that the XDS data is not being updated
during the READ operation. The result is a meaningless combination of two unrelated XDS data packets. If a
bad checksum is encountered, the READ operation should be repeated.
ABLE
OTE
: Banks 2 and 3 are 33 bytes in length. Byte 32 of these banks contains an 8 bit checksum. The checksum
5. Z86230 I
S
Descriptions
A general-purpose bank used to read the Z86230-defined internal registers. The
register to be read from Bank 0 is set up manually using the READ SELECT
commands, RDS1 and RDS2. These commands load the selected data byte (or pair
of bytes) into the first location(s) of Bank 0, and set the DAV bit to indicate the
availability of data.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the Program Blocking registers and permits direct,
multibyte reading of internal registers 08h through 11h. These registers are
described in the internal register section. When it is selected, the sequence of bytes
read is SSR, followed by internal registers 08h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh,
10h, and 11h.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the XDS Program Name data from the most recently
received current class type 3 packet.
A special purpose bank provided to facilitate the reading of commonly accessed
data. This bank contains the XDS Network Name and Call Letter data. The first 26
bytes has the XDS Network Name from the most recently received XDS channel
class type 1 packet. Bytes 26 through 31 has the XDS Call Letters data from the
most recently received XDS channel class type 2 packet
ERIAL
2
C READ B
C
F
The Z86230 I
sequences output the Serial Status Register (
to be read is selected by sending the
READ
N
condition of either WRITE sequence above. Refer to the One Byte READ (Status Only)
in
OMMUNICATIONS
IGURE
OTE
I
I
Figure 5
2
2
C Two-Byte WRITE (Command & Data)
C One-Byte WRITE (Command)
: The Status Register RDY bit must be read and checked prior to the START
ANK
START
bank modes are available in the Z86230:
START
4. I
2
C Bus
S
2
for more information on reading the Status Register.
ELECT
C B
2
C bus supports
(WRITE=28h for the 1
US
Z86230—PRELIMINARY
(WRITE=28h for the 1
SLAVE ADDR
SLAVE ADDR
I
(RBS) C
NTERFACE
WRITE (C
OMMAND
OMMAND
st
READ
st
WRITE CMD
I
2
I
WRITE CMD
2
C Address and 2Ah for the 2
C Address and 2Ah for the 2
READ BANK SELECT
sequences up to 34 bytes in length. All
)
SSR
WRITE DATA
STOP
) as the first output byte. The data
nd
nd
I
2
I
2
C Address)
C Address)
STOP
(
RBS
PS000401-TVC0699
) command. Four
I
2
C B
US
O
PERATION
READ