AD9948KCPZRL Analog Devices Inc, AD9948KCPZRL Datasheet - Page 24

• Manufacturer Part Number: AD9948KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9948KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9948
APPLICATIONS INFORMATION
Circuit Configuration
The AD9948 recommended circuit configuration is shown in
Figure 21. Achieving good image quality from the AD9948
requires careful attention to PCB layout. All signals should be
routed to maintain low noise performance. The CCD output
signal should be directly routed to Pin 27 through a 0.1 µF
capacitor. The master clock CLI should be carefully routed to
Pin 25 to minimize interference with the CCDIN, REFT, and
REFB signals.
The digital outputs and clock inputs are located on Pins 2 to 13
and Pins 31 to 39, and should be connected to the digital ASIC
away from the analog and CCD clock signals. Placing series
resistors close to the digital output pins may help to reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
AD9948’s outputs can be selected to output data in gray code
format using the control register Bit D5. Gray coding will
help reduce potential digital transition noise compared with
binary coding.
The H1–H4 and RG traces should have low inductance to
avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand
on H1–H4 from the capacitive load of the CCD. If possible,
physically locating the AD9948 closer to the CCD will reduce
the inductance on these lines. As always, the routing path
should be as direct as possible from the AD9948 to the CCD.
SUPPLY
DRIVER
3V
VD/HD/HBLK INPUTS
+
OUTPUTS
4.7 F 0.1 F
CLP/BLK OUTPUT
DATA
10
(LSB) D0
DRVDD
DRVSS
NC
D1
D2
D3
D4
D5
D6 10
4
ANALOG
Figure 21. Recommended Circuit Configuration
SUPPLY
9
1
2
3
4
5
6
7
8
3V
PIN 1
IDENTIFIER
TOP VIEW
AD9948
0.1 F
–24–
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9948. This ground plane should be as continuous as
possible, particularly around Pins 23 to 30. This will ensure that
all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All high frequency decoupling capacitors
should be located as close as possible to the package pins. It is
recommended that the exposed paddle on the bottom of the
package be soldered to a large pad, with multiple vias connect-
ing the pad to the ground plane.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be a
4.7 µF or larger bypass capacitor for each main supply—AVDD,
RGVDD, HVDD, and DRVDD—although this is not necessary
for each individual pin. In most applications, it is easier to share
the supply for RGVDD and HVDD, which may be done as long
as the individual supply pins are separately bypassed. A separate
3 V supply may be used for DRVDD, but this supply pin should
still be decoupled to the same ground plane as the rest of the
chip. A separate ground for DRVSS is not recommended.
The reference bypass pins (REFT, REFB) should be decoupled
to ground as close as possible to their respective pins. The analog
input (CCDIN) capacitor should also be located close to the pin.
0.1 F
30
29
28
27
26
25
24
23
22
21
3
REFB
REFT
AVSS
CCDIN
AVDD
CLI
TCVDD
TCVSS
RGVDD
RG
+
4.7 F
4
0.1 F
SERIAL
INTERFACE
1 F
1 F
0.1 F
0.1 F
+
4.7 F
0.1 F
+
4.7 F
H1–H4
H DRIVER
SUPPLY
RG OUTPUT
CCD SIGNAL
MASTER CLOCK INPUT
RG DRIVER
SUPPLY
3V
ANALOG
SUPPLY
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