AD9948KCPZRL Analog Devices Inc, AD9948KCPZRL Datasheet - Page 4

• Manufacturer Part Number: AD9948KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9948KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9948
Model
AD9948KCP
AD9948KCPRL
AD9948KCPZ*
AD9948KCPZRL* –20°C to +85°C
*This is a lead free product.
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK (CLI) (See Figure 4)
CLPOB Pulsewidth (Programmable)*
SAMPLE CLOCKS (See Figure 6)
DATA OUTPUTS (See Figures 7a and 7b)
SERIAL INTERFACE
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD, TCVDD
HVDD, RGVDD
DVDD, DRVDD
Any VSS
Digital Outputs
CLPOB/PBLK, HBLK
SCK, SL, SDATA
RG
H1–H4
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature (10 sec)
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9948 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
rating only; functional operation of the device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI to Internal Pixel
SHP Rising Edge to SHD Rising Edge
Output Delay From Programmed Edge
Pipeline Delay
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Period Position
Temperature
Range
–20°C to +85°C
–20°C to +85°C
–20°C to +85°C
ORDERING GUIDE
With
Respect To
AVSS
HVSS, RGVSS
DVSS, DRVSS
Any VSS
DRVSS
DVSS
DVSS
RGVSS
HVSS
AVSS
(C
Package
Description Option
LFCSP
LFCSP
LFCSP
LFCSP
L
= 20 pF, f
Symbol
t
t
t
t
t
t
f
t
t
t
t
t
SCLK
CLI
ADC
CLIDLY
COB
S1
OD
LS
LH
DS
DH
DV
CLI
= 25 MHz, Serial Timing in Figure 3, unless otherwise noted.)
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Package
CP-40
CP-40
CP-40
CP-40
–4–
Min
40
16
2
17
10
10
10
10
10
10
Max
+3.9
+3.9
+3.9
+0.3
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
RGVDD + 0.3
HVDD + 0.3
AVDD + 0.3
150
300
THERMAL CHARACTERISTICS
Thermal Resistance
40-Lead LFCSP Package
*
soldered to the board.
JA
Typ
20
6
20
20
6
11
JA
is measured using a 4-layer PCB with the exposed paddle
= 27°C/W*
Unit
V
V
V
V
V
V
V
V
V
V
°C
°C
Max
24
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
REV. 0