AD9949KCP Analog Devices Inc, AD9949KCP Datasheet - Page 21

IC CCD SIGNAL PROCESSOR 40-LFCSP

AD9949KCP

Manufacturer Part Number
AD9949KCP
Description
IC CCD SIGNAL PROCESSOR 40-LFCSP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet

Specifications of AD9949KCP

Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Sample Rate
36MSPS
Input Voltage Range
0.5V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Resolution
12b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
40
Package Type
LFCSP EP
Number Of Channels
1
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant

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HORIZONTAL CLAMPING AND BLANKING
The AD9949’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the
dark pixel clamping and blanking patterns to be changed at
each stage of the readout to accommodate different image
transfer timing and high speed line shifts.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 21. These two signals are independently
programmed using the parameters shown in Table 18. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
Table 18. CLPOB and PBLK Individual Sequence Parameters
Parameter
Polarity
Toggle Position 1
Toggle Position 2
Table 19. HBLK Individual Sequence Parameters
Parameter
HBLKMASK
Toggle Position 1
Toggle Position 2
Toggle Position 3
Toggle Position 4
Toggle Position 5
Toggle Position 6
CLPOB
HBLK
PBLK
HD
HD
PROGRAMMABLE SETTINGS:
1. FIRST TOGGLE POSITION = START OF BLANKING.
2. SECOND TOGGLE POSITION = END OF BLANKING.
1
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
Length
1b
12b
12b
12b
12b
12b
12b
1b
12b
Length
12b
1
2
BLANK
ACTIVE
Range
High/Low
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Pixel Location
Range
High/Low
0 to 4095 Pixel Location
0 to 4095 Pixel Location
2
3
Figure 22. Horizontal Blanking (HBLK) Pulse Placement
Figure 21. Clamp and Preblank Pulse Placement
Rev. B | Page 21 of 36
Description
Starting Polarity of Clamp and PBLK Pulses for Sequences 0 to 3.
First Toggle Position within the Line for Sequences 0 to 3.
Second Toggle Position within the Line for Sequences 0 to 3.
Description
Masking Polarity for H1 for Sequences 0 to 3 (0 = H1 Low, 1 = H1 High).
First Toggle Position within the Line for Sequences 0 to 3.
Second Toggle Position within the Line for Sequences 0 to 3.
Third Toggle Position within the Line for Sequences 0 to 3.
Fourth Toggle Position within the Line for Sequences 0 to 3.
Fifth Toggle Position within the Line for Sequences 0 to 3.
Sixth Toggle Position within the Line for Sequences 0 to 3.
signals are active low and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing shown in Figure 22 is similar
to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the
start and the stop positions of the blanking period. Additionally,
there is a polarity control, HBLKMASK, which designates the
polarity of the horizontal clock signals H1 to H4 during the
blanking period. Setting HBLKMASK high sets H1 = H3 = low
and H2 = H4 = high during the blanking, as shown in Figure 23.
Up to four individual sequences are available for HBLK.
BLANK
ACTIVE
...
...
...
...
AD9949

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