FIN24CGFX Fairchild Semiconductor, FIN24CGFX Datasheet
FIN24CGFX
Specifications of FIN24CGFX
FIN24CGFXTR
Available stocks
Related parts for FIN24CGFX
FIN24CGFX Summary of contents
Page 1
... LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive Ordering Information Package Order Number Number FIN24CGFX BGA042 FIN24CMLX MLP040 Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. µSerDes is a trademark of Fairchild Semiconductor Corporation. ...
Page 2
... Functional Block Diagram CKREF STROBE DP[m+1:24] DP[1:m] Note: I Control CKP S1 S2 DIRI ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq. Direction Control Control oe Power Down Control Figure 1 ...
Page 3
... The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Number of ...
Page 4
... Connection Diagrams Figure 2. Terminal Assignments for MLP (Top View (Top View) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 DP[9] 1 DP[10] 2 DP[11] 3 DP[12 DDP CKP 6 DP[13] 7 DP[14] 8 DP[15] 9 DP[16] 10 Pin Assignments DP[9] DP[7] DP[5] B DP[11] DP[10] DP[6] C CKP DP[12] DP[8] D DP[13] DP[14] ...
Page 5
... Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten. ...
Page 6
... MODE 3 ( “1”). In this mode, 22 bits can be sent in either direction. When operating in a 2-bit control mode, serialized bits 21 and 22 appear on outputs 23 and 24 of the deserializer. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device ...
Page 7
... CKS0 No Data Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase ...
Page 8
... DSO CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH ...
Page 9
... DP[1:24] WORD n-2 Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data ...
Page 10
... Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 bidirectional pins should be connected to GND through a high-value resistor FIN24C devices is configured as an unidirectional serializer, unused data I/O can be treated as unused inputs ...
Page 11
... Generates and transmits serialized data on the DS signals source synchronous with CKSO. 5. Generates an embedded word clock for each strobe signal. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Mode 0 state ( upon detecting a LOW on both the S1 and S2 signals. Any of the other modes are DS+ ...
Page 12
... Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. ■ ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 FIN24C CKREF CKSO CKSI ...
Page 13
... CKSO, CKSI, DSO to GND Recommended Operating Conditions Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Parameter Parameter 13 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V Continuous -65 +150 °C +150 ° ...
Page 14
... Voltage is referenced to GROUND unless otherwise specified (except ΔV and the difference in device ground levels between the CTL driver and the CTL receiver. GO ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions I = –2 3.3 ± 0.3 OH DDP V = 2.5 ± ...
Page 15
... Dynamic Serializer DD_SER2 Power Supply Current DD_SER2 DDA DDS ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions All DPI and Control Inputs CKREF DIRI = 1 All DPI and Control Inputs CKREF DIRI = 1 All DPI and Control Inputs CKREF DIRI = 1 All DPI and Control Inputs ...
Page 16
... PDV t Output Rise Time ROLH (20% to 80%) t Output Fall Time ROHL (80% to 20%) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions See Figure 20 CKREF does not equal STROBE See Figure 20 See Figure 20 CKREF x 26 DIRI = 1, See Figure 5MHz) CKREF Does Not Equal STROBE ...
Page 17
... Capacitance of Input Only Signals, IN CKREF, STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins IO DP[1:12] C Capacitance of Differential I/O Signals IO-DIFF ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 = 2.775V and T = 25°C. Positive current values refer to the current flowing into Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW ...
Page 18
... Maximum power is measured at the maximum V Typical values are measured 2.775V TLH 80% 20% V DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 17. CTL Output Load and Transition Times ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 DS+ DUT DS- Figure 15. CTL Input Common Mode Test Circuit T 999h b ...
Page 19
... EN_DES = “1”, CKSI, and DSI are valid signals. Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters t TCCD STROBE V DD/2 CKS0- V DIFF CKS0+ Note: STROBE = CKREF Figure 23. Serializer Clock Propagation Delay ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) Data t HTC t PDV 50% 25% t RCOL CKSI CKSI+ Figure 24 ...
Page 20
... Figure 27. PLL Loss of Clock Disable Time t PLZ(HZ DS+,CKS0+ HIGH-Z DS-,CKS0- Note: CKREF must be active and PLL must be stable. Figure 29. Serializer Enable and Disable Time ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) CKSO- t H_DS CKSO+ DSO+ DSO- Note: Data is typically edge aligned with the clock. ...
Page 21
... A, B, and C). 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0 Min. ±0.1 ±0.1 ± ...
Page 22
... A, B, and C). 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued Min. ±0.1 ± ...
Page 23
... A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 3.50 2X 0.10 C (0.6) 4.50 0.5 0.89±0.082 0.45±0.05 0.21± ...
Page 24
... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (DATUM A) 24 www.fairchildsemi.com ...
Page 25
... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ GlobalOptoisolator™ Bottomless™ GTO™ Build it Now™ HiSeC™ ...