ISL54105CRZ Intersil, ISL54105CRZ Datasheet - Page 12

• Manufacturer Part Number: ISL54105CRZ
• Description: IC TMDS REGENERATOR 72-QFN
• Manufacturer: Intersil

Specifications of ISL54105CRZ

• Applications: Multimedia Displays, Test Equipment
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 72-VFQFN Exposed Pad
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUTPUT SKEW
162.5Mpixels/s)
(4 bits/2.5ns at
of skew relative to the incoming green and blue. The FIFO’s
quantization (worst case) increases the total skew to 4.0 bits.
While increasing skew is not desirable, DVI and HDMI
receivers are required to have a minimum of 6 bits of
inter-pair skew tolerance, so the addition of 2 bits of skew is
only a problem with the most pathological cables and
transmitters. It does, however, limit the number of ISL54105s
that can be put in series (although statistically, it is unlikely
that all the skews would line up in a worst-case
configuration).
PCB Layout Recommendations
Because of the high speed of the TMDS signals, careful
PCB layout is critical to maximize performance. The
following guidelines should be adhered to as closely as
possible:
• All TMDS pair traces should have a characteristic
• Avoid vias for all 3 high speed TMDS pairs. Vias add
• For each TMDS channel, the trace lengths of the 3 TMDS
• The trace length of the clock pair is not critical at all.
in this example)
INPUT SKEW
(2.3 bits/1.4ns
FIGURE 11. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
impedance of 50Ω with respect to the power/ground
planes and 100Ω with respect to each other. Failure to
meet this requirement will increase reflections, shrinking
the available eye.
inductance which causes a discontinuity in the
characteristic impedance of the trace. Keep all the traces
on the top (or the bottom) of the PCB. The TMDS clock
can have vias if necessary, since it is lower speed and less
critical. If you must use a via, ensure the vias are
symmetrical (put identical vias in both lines of the
differential pair).
pairs (0, 1 and 2) should ideally be the same to reduce
inter channel skew introduced by the board.
Since the clock is only used as a frequency reference, its
phase/delay is inconsequential. In addition, since the
TMDS clock frequency is 1/10th the pixel rate, the clock
signal itself is much more noise-immune. So liberties
Bit 5
Bit 4
Bit 8
Bit 7
Bit 7
Bit 7
FOR INPUTS WITH MODERATE TO LARGE
SKEW
Bit 4
Bit 6
Bit 6
Bit 3
Bit 6
Bit 7
Bit 3
Bit 2
Bit 6
Bit 5
Bit 5
Bit 5
Bit 2
Bit 4
Bit 4
Bit 1
Bit 4
Bit 5
12
Bit 1
Bit 3
Bit 3
Bit 0
Bit 3
Bit 4
Bit 0
Bit 9
Bit 3
Bit 2
Bit 2
Bit 2
Bit 9
Bit 8
Bit 1
Bit 1
Bit 1
Bit 2
Bit 8
Bit 7
Bit 1
Bit 0
Bit 0
Bit 0
Bit 7
Bit 9
Bit 9
Bit 6
Bit 9
Bit 0
Bit 6
Bit 8
Bit 8
Bit 5
Bit 8
Bit 9
Bit 5
ISL54105
Bit 4
Bit 8
Bit 7
Bit 7
Bit 7
• Minimize capacitance on all TMDS lines. The lower the
• Maintain a constant, solid ground (or power) plane under
• Ideally each supply should be bypassed to ground with a
(such as vias and circuitous paths) can be taken when
routing the clock lines.
capacitance, the sharper the rise and fall times.
the 3 high speed TMDS signals. Do not route the signals
over gaps in the ground plane or over other traces.
0.1µF capacitor. Minimize trace length and vias to
minimize inductance and maximize noise rejection.
Figure 12 demonstrates a common but non-ideal PCB
layout and its equivalent circuit. The additional trace
resistance between the bypass capacitor and the power
supply/IC reduces its effectiveness. Figure 13
demonstrates a better layout. In this case there is still
series trace resistance (it is impossible to completely
eliminate it), but now it is being put to good use, as part of
a “T” filter, attenuating supply noise before it gets to the IC,
and reducing the amount of IC-generated noise that gets
injected into the supply. Follow the good supply bypassing
rules shown in Figure 13 to the extent possible.
FIGURE 12. SUB-OPTIMAL BYPASS CAPACITOR LAYOUT
V
+
C
BYPASS
EQUIVALENT CIRCUIT
VIAS
GND
TO
C
POWER PLANE
R
BYPASS
TRACE
GROUND PLANE
POWER
PLANE
VIA TO
R
R
VIA
TRACE
V
GND
+
GND
V
IC
+
IC
June 11, 2008
FN6723.0