SI2493-D-FS Silicon Laboratories Inc, SI2493-D-FS Datasheet - Page 23

• Manufacturer Part Number: SI2493-D-FS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-D-FS

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A block diagram of the UART in the serial interface mode is shown in Figure 5.
.
2.2.4. Parallel and SPI Interface Operation
Refer to "2.1. Resetting the Device" on page 11 for interface selection. The parallel interface has an 8-bit data bus
and a single address bit. The SPI likewise operates with 8-bit data transfers, using a single address bit. When the
parallel or SPI interface mode is selected, the modem must be configured for a DTE interface or 8N1 only. The host
processor must calculate parity for the MSB. The modem sends bits as received by the host and does not calculate
parity. Refer to "Appendix C—Parallel/SPI Interface Software Implementation" on page 290 for detailed parallel or
SPI interface application information.
The parallel or SPI interface uses the FIFOs to buffer data in the same way as in UART mode, with the addition of
Hardware Interface Registers 0 (HIR0) and Hardware Interface Register 1 (HIR1). The Hardware Interface
Registers were formerly called Parallel Interface Registers (PIR0 and PIR1) in older products, because those
products would support only a parallel interface. Flow control must be implemented by monitoring REM and TXE in
HIR1. There is no protection against FIFO overflow. Data transmitted when the transmit FIFO is full are lost.
Figure 6 shows the interaction of the transmit and receive FIFOs with the Hardware (Parallel) Interface Registers in
the case of a parallel interface. The arrangement is similar when the SPI interface is selected. Table 21 on page 25
shows a bit map of HIR0 and HIR1.
UART oriented control lines, such as RTS and CTS, are not used in Parallel and SPI Interface mode. They are
replaced by bits in the HIR1 register.
SPI and parallel operation only supports 8-bit data words. The longer words that are implied by the \B5 (8P1) & \B6
8X1 commands are not allowed. These commands should not be used.
TX FIFO
Register
TX Shift
TXD
(10)
Figure 5. UART Serial Interface
CTS
(11)
CONTROL
RTS
(8)
Rev. 1.3
MUX
11 Bits
to Data Bus
(16)
INT
RX Shift
Register
RX FIFO
RXD
(9)
AN93
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