SI2493-D-FS Silicon Laboratories Inc, SI2493-D-FS Datasheet - Page 51

• Manufacturer Part Number: SI2493-D-FS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-D-FS

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4.1. ISOmodem Layout Check List
Table 34 is a checklist that the designer can use during the layout process to ensure that all the recommendations
in this application note have been implemented. Additionally, Figure 21 provides an annotated diagram of all
relevant layout guidelines for the SI3054 CNR/AMR/ACR applications. See "10.4.2. Safety" on page 254 for
information about design for safety compliance.
P
11
#
1
2
3
4
1
12
C27
C50
Y1
C26
U1 and U2 are placed so that pins 9–16 of U1 are facing pins 1–8 of U2. C1 and C2
are placed directly between U1 and U2.
Place U1, U2, C1, and C2 so that the recommended minimum creepage spacing for
the target application is implemented. R12 and R13 should be close to U1.
C1 and C2 should be placed directly between U1 and U2. Short, direct traces should
be used to connect C1 and C2 to U1 and U2. These traces should not be longer than
two inches and should be minimized in length. Place C2 such that its accompanying
trace to the C2B pin (pin 6) on the Si3018 is not close to the trace from R7 to the
RNG1 pin on the Si3018 (pin 8).
Place R7 and R8 as close as possible to the RNG1 and RNG2 pins (pins 8 and 9),
ensuring a minimum trace length from the RNG1 or RNG2 pin to the R7 or R8 resistor.
In order to space the R7 component further from the trace from C2 to the C2B pin, it is
acceptable to orient it 90 degrees relative to the RNG1 pin (pin 8).
2
*Note: Do NOT use ferrite
beads in place of R12 and
R13.
C51
12
Note: Encircled references are described in the numbered paragraphs in Appendix A.
11
1
2
5
6
7
11
XTALI
XTALO
VDD3.3
GND
VDDA
U1 Si24HS
VDD3.3
VDDB
GND
C1A
C1B
This is not a complete schematic. Only critical component placement and nets are drawn.
12
21
20
19
14
13
3A
C53
R12*
R13*
3C
C52
Figure 21. Illustrated Layout Guidelines
12
2
3E
2
C1
C2
3B
4G
9C
Table 34. Layout Checklist
4A
C5
C4
7B
+
3A
3E
4F
3E
R7
1
2
3
4
5
6
7
8
QE
DCT
RX
IB
C1B
C2B
VREG
RNG1
4C
4B
U2
9A
Layout Items
C7
R9
Rev. 1.3
VREG2
RNG2
DCT2
DCT3
9B
Si3018
IGND
QE2
QB
SC
3E
4F
10
16
15
14
13
12
11
10
9
9C
R2
3E
10
R8
4D
C6
9C
4E
6
5
8D
-
Q5
Q4
8C
8D
C3
+
D1
1
7B
FB2
FB1
Traces, pad sites and vias
enclosed in box are in the DAA
section, and must be separated
from all other circuits by 5 mm.
7C
2
C9
7A
C8
7C 7B
2
R16
R15
RV1
AN93
RING
TIP
Required
51