SI2493-D-FS Silicon Laboratories Inc, SI2493-D-FS Datasheet - Page 25

• Manufacturer Part Number: SI2493-D-FS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-D-FS

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.2.4.1. Hardware Interface Register 0
Hardware Interface Register 0 (HIR0) is the eight-bit wide read/write location where modem data and commands
are exchanged with the host. Writing a byte to the HIR0 adds that byte to the modem’s transmit FIFO (AT
command buffer in command mode or data transmission in data mode). If data are available (modem data in data
mode or command responses, such as OK, in command mode), reading from the HIR0 fetches data from the
modem’s receive FIFO. The maximum burst data rate is approximately 350 kbps (45 kBps).
2.2.4.2. Hardware Interface Register 1
Hardware Interface Register 1 (HIR1) contains various status and control flags for use by the host to perform data
flow control, to escape to command mode and to query various interrupt conditions. The HIR1 bit map is described
in Table 22. This register is reset to 0x63.
Bit 7 (RXF) is a read/write bit that gives the status of the 12-byte deep receive FIFO. If RXF = 0, the receive FIFO
contains less than 10 bytes. If RXF = 1, the receive FIFO contains more than 9 bytes and is full or almost full.
Writing RXF = 0 clears the interrupt.
*Note: REM and INT are read-only bits.
Bit
A0
7
6
5
4
3
2
1
0
0
0
1
1
Name
INTM
RD
REM
RXF
ESC
RTS
CTS
TXE
INT
0
1
0
1
WR
1
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Action
Read
Read
Write
Write
Reset
Table 21. Hardware Interface Register Bit Map
0
1
1
0
0
0
1
1
Table 22. Hardware Interface Register 1
Register
Function
Receive FIFO Almost Full
Transmit FIFO Almost Empty
Receive FIFO Empty
Interrupt Mask
0 = INT pin triggered on rising edge of RXF or TXE only
1 = INT pin triggered on rising edge of RXF, TXE or INT (bit 3 below)
Interrupt
0 = No interrupt
1 = Interrupt triggered
Escape
Request-to-Send (active low) — Deprecated — for flow control, use the
TXE and REM bits for polling- or interrupt-based communication.
This bit must be written to zero.
Clear-to-Send (active low) — Deprecated — for flow control, use the TXE
and REM bits for polling- or interrupt-based communication.
HIR0
HIR1
RXF
RXF
D7
Rev. 1.3
TXE
TXE
D6
Modem data or command from receive FIFO
Modem data or command to transmit FIFO
*Note
REM
D5
INTM
INTM
D4
*Note
INT
D3
ESC
ESC
D2
RTS
RTS
D1
AN93
CTS
n/a
D0
25